公开(公告)号：US20240143403A1

公开(公告)日：2024-05-02

申请号：US18354601

申请日：2023-07-18

Applicant: ZHEJIANG LAB

Inventor： Huifeng ZHANG ,  Congqi SHEN ,  Tao ZOU ,  Jun ZHU ,  Ruyun ZHANG ,  Qi XU ,  Hanguang LUO ,  Xingchang GUO

IPC: G06F9/50 ,  G06N20/00

CPC classification number: G06F9/5038 ,  G06N20/00

Abstract: A method, an apparatus and a medium for optimizing allocation of switching resources in the polymorphic network. The method selects the ASIC switching chip, FPGA and PPK software switching on the polymorphic network element based on machine learning, and specifically comprises the following steps: manually pre-configuring, formulating basic rules for polymorphic software and hardware co-processing; offline learning, designing training configuration in the offline learning stage to capture different switching resource usage variables, running experiments to generate the original data of a training classifier, and using the generated performance indices to train the model offline; and online reasoning, obtaining switching resource allocation advises, and updating modality codes according to the switching resource allocation advises.

公开(公告)号：US20240020455A1

公开(公告)日：2024-01-18

申请号：US18351464

申请日：2023-07-12

Applicant: ZHEJIANG LAB

Inventor： Zhiquan WAN ,  Shunbin LI ,  Ruyun ZHANG ,  Weihao WANG ,  Qingwen DENG

IPC: G06F30/398 ,  G06F30/392

CPC classification number: G06F30/398 ,  G06F30/392 ,  G06F2117/12

Abstract: The present disclosure relates to software-defined methods and apparatuses for designing a wafer-level switching system, including: determining wafer-level switching system layout constraints; constructing a target wafer-level switching system and determining parameters, and designing a logical topology of a switching network; designing a layout of the switching chiplets on the wafer substrate; respectively designing interface structures of external chiplets and internal chiplets; configuring a switching mode and an enable state of each port of the switching chiplets; ending the process when the target logical topology can be achieved by the wafer-level switching system; otherwise, reconstructing a logical topology of a switching network and mapping it to the substrate.

公开(公告)号：US20230236807A1

公开(公告)日：2023-07-27

申请号：US17979752

申请日：2022-11-02

Applicant: ZHEJIANG LAB

Inventor： Lei XUE ,  Tao ZOU ,  Ruyun ZHANG

IPC: G06F8/30 ,  G06F9/48 ,  G06F8/41

CPC classification number: G06F8/37 ,  G06F9/4881 ,  G06F8/447

Abstract: A software and hardware collaborative compilation processing method and system. The system comprises an environment configurator, a command parser, a code filler, a scheduler and a heterogeneous target system, wherein the code filler is configured for obtaining the source program path of a user, reading source codes and identifying the heterogeneous target system according to a macro definition, complementing the codes related to the heterogeneous target system, carrying out primary filling and secondary filling on the source codes; the scheduler is configured for realizing compilation scheduling and execution scheduling functions respectively; the heterogeneous target system is configured for compiling and processing user modal data, and comprises at least two heterogeneous target subsystems; each target subsystem comprises a target-related middle-end compiler, a back-end compiler and a target-related running environment.

公开(公告)号：US20240214324A1

公开(公告)日：2024-06-27

申请号：US18389820

申请日：2023-12-20

Applicant: ZHEJIANG LAB

Inventor： Xiaoyu YI ,  Yuan LIANG ,  Geyang XIAO ,  Xingchang GUO ,  Tao ZOU ,  Ruyun ZHANG ,  Linlin YAN

IPC: H04L47/6275 ,  H04L47/12

CPC classification number: H04L47/6275 ,  H04L47/12

Abstract: A traffic alarm method and apparatus based on a programmable switch, a device and a medium. The method monitors traffic with different priorities, when the traffic is greater than or equal to a threshold, the programmable switch may give a real-time alarm on a data plane and return low priority traffic information in a current network back to a sending end, and the sending end may adjust a task priority through alarm information. The present disclosure uses a programmable switch device, the lower priority traffic information may be alarmed to the sending end in real time on the data plane without passing through a controller, an alarm delay is significantly reduced, the sending end may adjust a sending rate timely, real-time scheduling of network traffic is achieved, high priority traffic transmission is ensured, and meanwhile link utilization is improved.

公开(公告)号：US20240061663A1

公开(公告)日：2024-02-22

申请号：US18495707

申请日：2023-10-26

Applicant: ZHEJIANG LAB

Inventor： Lei XUE ,  Tao ZOU ,  Ruyun ZHANG ,  Jun ZHU

IPC: G06F8/41 ,  G06F9/445

CPC classification number: G06F8/443 ,  G06F9/44505

Abstract: The present disclosure discloses a compiling system for a compiling system and a compiling method for a programmable network element. Aiming at the diversified requirements of network modals for the underlying hardware resources, the system realizes the integration and fusion mechanism of computing/storage/forwarding/security, and abstracts network element equipment including heterogeneous hardware resources and isomeric hardware resources into a logical network element irrelevant to the underlying hardware; performs advanced abstract encapsulation on the heterogeneous hardware resources and isomeric hardware resources, supports flexible calling of underlying hardware and software resources, uses the technology of functional equivalent replacement between heterogeneous hardware resources and isomeric hardware resources, realizes switching and co-processing of network modals among hardware resources according to actual requirements, allocates heterogeneous hardware resources according to modal characteristics, and calls various compilers to automatically generate and optimize modal packet processing pipelines.

公开(公告)号：US20240006372A1

公开(公告)日：2024-01-04

申请号：US18328797

申请日：2023-06-05

Applicant: ZHEJIANG LAB

Inventor： Weihao WANG ,  Shunbin LI ,  Guandong LIU ,  Ruyun ZHANG ,  Qinrang LIU ,  Zhiquan WAN ,  Jianliang SHEN

IPC: H01L23/00

CPC classification number: H01L24/81 ,  H01L24/11 ,  H01L24/14 ,  H01L2224/1403 ,  H01L2224/145 ,  H01L2224/14131 ,  H01L2224/11462

Abstract: A system-on-wafer structure and a fabrication method. The structure includes a wafer substrate, an integrated chiplet, a system configuration board and a thermal module. The wafer substrate and the integrated chiplet are bonded through a wafer micro bump array and a chiplet micro bump array. The wafer substrate and the system configuration board are bonded through a copper pillar array on wafer substrate topside and a pad on system configuration board backside. A molding layer is provided between the wafer substrate and the system configuration board, and is configured to mold the wafer substrate, the integrated chiplet and the copper pillar array. Integrated chiplet are electrically connected to each other through a re-distributed layer in wafer substrate. The integrated chiplet is electrically connected to the system configuration board through the re-distributed layer and the copper pillar array. The thermal module is attached to the backside of the wafer substrate.

公开(公告)号：US20230421500A1

公开(公告)日：2023-12-28

申请号：US18092939

申请日：2023-01-04

Applicant: ZHEJIANG LAB

Inventor： Congqi SHEN ,  Xingchang GUO ,  Hanguang LUO ,  Qi XU ,  Tao ZOU ,  Ruyun ZHANG

IPC: H04L45/7453 ,  H04L67/63 ,  H04N21/232

CPC classification number: H04L45/7453 ,  H04N21/232 ,  H04L67/63

Abstract: A content store-and-forward method, apparatus, an electronic apparatus and a storage medium, the method comprising the following steps: receiving an interest packet in a named data network; forwarding the interest packet to a storage node, so that the storage node looks up the corresponding content, and packages the content into a data packet containing the hash value of the name identifier and the corresponding content; receiving the data packet forwarded by the storage node; forwarding the data packet to an interest packet port, wherein the interest packet port is a port that has once received the name identifier corresponding to the content in the data packet; forwarding another data packet to the storage node, so that the storage node parses the hash value and the content of the name identifier in the another data packet, and stores the hash value of the name identifier and the corresponding content.

公开(公告)号：US20230418836A1

公开(公告)日：2023-12-28

申请号：US17981368

申请日：2022-11-04

Applicant: ZHEJIANG LAB

Inventor： Peilei WANG ,  Ruyun ZHANG ,  Tao ZOU ,  Shunbin LI ,  Peilong HUANG

IPC: G06F16/27 ,  H04L67/56 ,  G06F9/54 ,  G06F16/25

CPC classification number: G06F16/27 ,  H04L67/56 ,  G06F9/54 ,  G06F16/256

Abstract: Disclosed are an input/output proxy method and apparatus for a mimic Redis database. Through a pseudo server module, it is ensured that the interface of the Redis database is consistent with the external interface of the native Redis, so that it is convenient to implant the Redis database into arbitrary Redis application scenarios; the isolation of the modules inside is realized by independent processes, thus facilitating independent development, maintenance and expansion; and the synchronization function is integrated into the input/output proxy to achieve resource reuse; for the synchronization function, the random credit attenuation mechanism is cleverly utilized to ensure the synchronization function while taking into account the saving of resources.

公开(公告)号：US20230169063A1

公开(公告)日：2023-06-01

申请号：US17824349

申请日：2022-05-25

Applicant: ZHEJIANG LAB

Inventor： Peilei WANG ,  Ruyun ZHANG ,  Tao ZOU ,  Peilong HUANG

IPC: G06F16/23 ,  G06F16/27 ,  G06F16/21

CPC classification number: G06F16/2365 ,  G06F16/275 ,  G06F16/21

Abstract: The disclosure discloses a mimetic database-based network operating system design method, including: designing a mimetic data structure; designing a mimetic data object; designing a synchronization mechanism and a decision mechanism, designing a mimetic database safe storage command processing system, and designing a classification storage mechanism for interacting data between service modules and a master database in a network operating system. By means of vertical hierarchy and horizontal classification, the problem of compatibility of the database subjected to mimetic transformation and a network operating system is solved. By means of a memory random distribution storage mechanism and a memory hardware heterogeneous storage mechanism, the cost caused by mimetic transformation can be reduced, and the cost is controllable while the safety is improved.