公开(公告)号：US12248423B2

公开(公告)日：2025-03-11

申请号：US18163620

申请日：2023-02-02

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Buheng Xu ,  Dong Yu ,  Philip Ng ,  Lianji Cheng

IPC: G06F13/42

Abstract: An apparatus includes logic circuitry that selects a retag transaction identifier for an original transaction identifier of an incoming transaction request, based on a plurality of sub-groups of retag tracking data. Each sub-group of retag tracking data is associated with a corresponding sub-group of retag transaction identifiers in a group of retag transaction identifiers. The logic circuitry retags the incoming transaction request with the selected retag transaction identifier (ID) by replacing the original transaction identifier associated with the incoming transaction request and sends the retagged incoming transaction request to a target. A returned response is received from the target. The retag transaction ID in the returned response is removed and replaced with the original transaction ID before being sent as a reply to the requesting unit. Associated methods are also presented.

公开(公告)号：US12190847B2

公开(公告)日：2025-01-07

申请号：US17407981

申请日：2021-08-20

Applicant: ATI Technologies ULC

Inventor： Keith Lee ,  David I. J. Glen ,  Jie Zhou ,  Yuxin Chen

IPC: G09G5/02 ,  G09G5/06

Abstract: Systems, apparatuses, and methods for reducing three dimensional (3D) lookup table (LUT) interpolation error while minimizing on-chip storage are disclosed. A processor generates a plurality of mappings from a first gamut to a second gamut at locations interspersed throughout a 3D representation of the pixel component space. For example, in one implementation, the processor calculates mappings for 17×17×17 vertices within the 3D representation. Other implementations can include other numbers of vertices. Rather than increasing the number of vertices to reduce interpolation error, the processor calculates mappings for centroids of the sub-cubes defined by the vertices within the 3D representation of the first gamut. This results in a smaller increase to the LUT size as compared to increasing the number of vertices. The centroid mappings are used for performing tetrahedral interpolation to map source pixels in the first gamut into the second gamut with a reduced amount of interpolation error.

公开(公告)号：US20250004494A1

公开(公告)日：2025-01-02

申请号：US18345985

申请日：2023-06-30

Applicant: ATI Technologies ULC

Inventor： Carlos Javier Moreira ,  Michael McLean ,  Philip Ng

IPC: G06F1/04

Abstract: The disclosed device includes an input/output (I/O) system clock configured to operate at one of a plurality of clock states and a control circuit configured to dynamically adjust a clock state of the I/O system clock. The control circuit can update an activity level of a current clock state based at least on I/O traffic activity and, in response to the activity level going beyond an activity range for the current clock state, transition the I/O system clock to a neighboring clock state. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US20240422317A1

公开(公告)日：2024-12-19

申请号：US18334963

申请日：2023-06-14

Applicant: ATI Technologies ULC

Inventor： Jin Li ,  Crystal Yeong-Pian Sau

IPC: H04N19/124 ,  G06T5/40 ,  H04N19/159 ,  H04N23/56

Abstract: A technique for performing video operations is provided. The technique includes characterizing a frame as a flash frame; setting the flash frame as a non-intra frame; prohibiting encoding of frames other than the flash frame with reference to the flash frame; and applying a positive quantization parameter (“QP”) offset to the flash frame.

公开(公告)号：US20240419358A1

公开(公告)日：2024-12-19

申请号：US18665840

申请日：2024-05-16

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Joseph L. GREATHOUSE ,  Sean KEELY ,  Alan D. SMITH ,  Anthony ASARO ,  Ling-Ling WANG ,  Milind N NEMLEKAR ,  Hari THANGIRALA ,  Felix KUEHLING

IPC: G06F3/06 ,  G06F13/28

Abstract: A method for hardware management of DMA transfer commands includes accessing, by a first DMA engine, a DMA transfer command and determining a first portion of a data transfer requested by the DMA transfer command. Transfer of a first portion of the data transfer by the first DMA engine is initiated based at least in part on the DMA transfer command. Similarly, a second portion of the data transfer by a second DMA engine is initiated based at least in part on the DMA transfer command. After transferring the first portion and the second portion of the data transfer, an indication is generated that signals completion of the data transfer requested by the DMA transfer command.

公开(公告)号：US12164365B2

公开(公告)日：2024-12-10

申请号：US18146811

申请日：2022-12-27

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Gia Tung Phan ,  Ashish Jain ,  Shang Yang

IPC: G06F1/3296 ,  G06F12/0875 ,  G06T1/20 ,  G06T1/60

Abstract: An apparatus and method for efficiently managing power consumption among multiple, replicated functional blocks of an integrated circuit. An integrated circuit includes multiple, replicated functional blocks that use separate power domains. Data of a given type is stored in an interleaved manner among at least two of the multiple functional blocks. In one implementation, a prior static allocation determines that only a subset of the functional blocks store the data of the given type. In another implementation, each of the functional blocks stores the data of the given type, and when an idle state has occurred, data of the given type is moved between the multiple functional blocks until one or more functional blocks no longer store data of the given type. When a transition to the idle state has occurred, the functional blocks that do not store the data of the given type are transitioned to a sleep state.

公开(公告)号：US12148715B2

公开(公告)日：2024-11-19

申请号：US17643698

申请日：2021-12-10

Applicant: ATI Technologies ULC

Inventor： Roden Topacio

IPC: H01L23/00

Abstract: An electronic device includes a substrate, an electronic component, a structure, and an adhesive. The substrate has a proximal surface. The electronic component includes at least one die, wherein the electronic component is attached to the substrate. The structure has a proximal surface adjacent to proximal surface of the substrate. A feature extends from the proximal surface of the structure or the substrate, and the adhesive contacts the feature and the proximal surfaces of the structure and the substrate. In another aspect, a process of forming the electronic device can include applying the adhesive, placing the substrate and structure adjacent to each other, wherein the adhesive contacts the feature and the proximal surfaces of the substrate and the substrate, and curing the adhesive.

公开(公告)号：US12148134B2

公开(公告)日：2024-11-19

申请号：US18309568

申请日：2023-04-28

Applicant: ATI Technologies ULC

Inventor： Jie Zhou ,  David I. J. Glen

IPC: G06K9/40 ,  G06T5/92 ,  H04N23/741

Abstract: There are many instances where a standard dynamic range (“SDR”) overlay is displayed over high dynamic range (“HDR”) content on HDR displays. Because the overlay is SDR, the maximum brightness of the overlay is much lower than the maximum brightness of the HDR content, which can lead to the SDR elements being obscured if those elements have at least some transparency. The present disclosure provides techniques including modifying the luminance of either or both of the HDR and SDR content when an SDR layer with some transparency is displayed over HDR content. A variety of techniques are provided. In one example, a fixed adjustment is applied to pixels of one or both of the SDR layer and the HDR layer. The fixed adjustment comprises decreasing the luminance of the HDR layer and/or increasing the luminance of the SDR layer. In another example, a variable adjustment is applied.

公开(公告)号：US20240371427A1

公开(公告)日：2024-11-07

申请号：US18310872

申请日：2023-05-02

Applicant: Advanced Micro Devices, Inc ,  ATI Technologies ULC

Inventor： Tsun-Ho Liu ,  Anwar Parvez Kashem ,  Pouya Najafi Ashtiani ,  Wei Qing Xie

IPC: G11C11/406 ,  G11C11/4074 ,  G11C11/4093

Abstract: A memory system includes a memory controller, a physical layer (PHY), and a memory (e.g., DRAM). Data is written to and read from the memory in different manners for different memory technologies, such as using different signals or signal timings for different memory technologies. Various runtime services specific to the memory technology are performed by the PHY rather than the memory controller. Examples of such runtime services include performing a training routine to train or re-train an interface between the PHY and the memory, performing a power management routine (e.g., to put the main memory in a self-refresh mode), and so forth.

公开(公告)号：US20240370375A1

公开(公告)日：2024-11-07

申请号：US18669053

申请日：2024-05-20

Applicant: ATI Technologies ULC

Inventor： Kostantinos Danny Christidis

IPC: G06F12/0873 ,  G06F12/14 ,  H04L12/46 ,  H04L41/08 ,  H04L49/90 ,  H04L61/25

Abstract: Apparatuses, systems and methods for routing requests and responses targeting a shared resource. A queue in a communication fabric is located in a path between the requesters and a shared resource. In some embodiments, the shared resource is a shared address translation cache stored in an endpoint. The physical channel between the queue and the shared resource supports multiple virtual channels. The queue assigns at least one entry to each virtual channel of a group of virtual channels where the group includes a virtual channel for each address translation request type from a single requester of the multiple requesters. When the at least one entry for a given requester is de-allocated, the queue allocates this entry only with requests from the assigned virtual channel even if the empty entry is the only available entry of the queue.