公开(公告)号：US20240330199A1

公开(公告)日：2024-10-03

申请号：US18517513

申请日：2023-11-22

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Anthony ASARO ,  Jeffrey G. CHENG ,  Anirudh R. ACHARYA

IPC: G06F12/1009 ,  G06F9/455

CPC classification number: G06F12/1009 ,  G06F9/45558 ,  G06F2009/45583 ,  G06F2212/657

Abstract: A processor supports secure memory access in a virtualized computing environment by employing requestor identifiers at bus devices (such as a graphics processing unit) to identify the virtual machine associated with each memory access request. The virtualized computing environment uses the requestor identifiers to control access to different regions of system memory, ensuring that each VM accesses only those regions of memory that the VM is allowed to access. The virtualized computing environment thereby supports efficient memory access by the bus devices while ensuring that the different regions of memory are protected from unauthorized access.

公开(公告)号：US20160371197A1

公开(公告)日：2016-12-22

申请号：US15254466

申请日：2016-09-01

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Anthony ASARO ,  Kevin NORMOYLE ,  Mark HUMMEL

IPC: G06F12/109 ,  G06F12/06 ,  G06F12/02

CPC classification number: G06F12/1036 ,  G06F12/0284 ,  G06F12/0646 ,  G06F12/08 ,  G06F12/10 ,  G06F12/109 ,  G06F2212/1012 ,  G06F2212/152 ,  G06F2212/656 ,  G06F2212/657

Abstract: A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a first processor configured for unified operation with a second processor. The method includes receiving a memory operation from a processor and mapping the memory operation to one of a plurality of memory heaps. The mapping produces a mapping result. The method also includes providing the mapping result to the processor.

公开(公告)号：US20160062911A1

公开(公告)日：2016-03-03

申请号：US14469928

申请日：2014-08-27

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Andrew G. KEGEL ,  Anthony ASARO

IPC: G06F12/10 ,  G06F12/02 ,  G06F13/28

CPC classification number: G06F12/1081 ,  G06F12/02 ,  G06F12/1009 ,  G06F12/1027 ,  G06F13/28 ,  G06F2212/1016 ,  G06F2212/2532 ,  G06F2212/65 ,  G06F2212/657 ,  G06F2212/68

Abstract: A device may receive a direct memory access request that identifies a virtual address. The device may determine whether the virtual address is within a particular range of virtual addresses. The device may selectively perform a first action or a second action based on determining whether the virtual address is within the particular range of virtual addresses. The first action may include causing a first address translation algorithm to be performed to translate the virtual address to a physical address associated with a memory device when the virtual address is not within the particular range of virtual addresses. The second action may include causing a second address translation algorithm to be performed to translate the virtual address to the physical address when the virtual address is within the particular range of virtual addresses. The second address translation algorithm may be different from the first address translation algorithm.

Abstract translation: 设备可以接收标识虚拟地址的直接存储器访问请求。 设备可以确定虚拟地址是否在虚拟地址的特定范围内。 该设备可以基于确定虚拟地址是否在虚拟地址的特定范围内来选择性地执行第一动作或第二动作。 第一动作可以包括当虚拟地址不在虚拟地址的特定范围内时，执行第一地址转换算法来将虚拟地址转换为与存储器设备相关联的物理地址。 第二动作可以包括当虚拟地址在虚拟地址的特定范围内时，执行第二地址转换算法来将虚拟地址转换为物理地址。 第二地址转换算法可能与第一地址转换算法不同。

公开(公告)号：US20200167291A1

公开(公告)日：2020-05-28

申请号：US16200446

申请日：2018-11-26

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Anthony ASARO ,  Richard E. GEORGE

IPC: G06F12/1009 ,  G06F11/07 ,  G06F11/36 ,  G06F9/30

Abstract: For one or more stages of execution of a software application at a first processor, a remap vector of a second processor is reconfigured to represent a dynamic mapping of virtual address groups to physical address groups for that stage. Each bit position of the remap vector is configured to store a value indicating whether a corresponding virtual address group is actively mapped to a corresponding physical address group. Address translation operations issued during a stage of execution of the software application are selectively processed based on the configuration of the remap vector for that stage, with the particular value at the bit position of the remap vector associated with the corresponding virtual address group controlling whether processing of the address translation operation is continued to obtain a virtual-to-physical address translation sought by the address translation operation or processing of the address translation operation is ceased and a fault is issued.

公开(公告)号：US20180011798A1

公开(公告)日：2018-01-11

申请号：US15695683

申请日：2017-09-05

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Anthony ASARO ,  Kevin NORMOYLE ,  Mark HUMMEL

IPC: G06F12/06 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10

CPC classification number: G06F12/1036 ,  G06F12/0284 ,  G06F12/0646 ,  G06F12/08 ,  G06F12/10 ,  G06F12/109 ,  G06F2212/1012 ,  G06F2212/152 ,  G06F2212/656 ,  G06F2212/657

Abstract: A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a first processor configured for unified operation with a second processor. The method includes receiving a memory operation from a processor and mapping the memory operation to one of a plurality of memory heaps. The mapping produces a mapping result. The method also includes providing the mapping result to the processor.

公开(公告)号：US20240419358A1

公开(公告)日：2024-12-19

申请号：US18665840

申请日：2024-05-16

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Joseph L. GREATHOUSE ,  Sean KEELY ,  Alan D. SMITH ,  Anthony ASARO ,  Ling-Ling WANG ,  Milind N NEMLEKAR ,  Hari THANGIRALA ,  Felix KUEHLING

IPC: G06F3/06 ,  G06F13/28

Abstract: A method for hardware management of DMA transfer commands includes accessing, by a first DMA engine, a DMA transfer command and determining a first portion of a data transfer requested by the DMA transfer command. Transfer of a first portion of the data transfer by the first DMA engine is initiated based at least in part on the DMA transfer command. Similarly, a second portion of the data transfer by a second DMA engine is initiated based at least in part on the DMA transfer command. After transferring the first portion and the second portion of the data transfer, an indication is generated that signals completion of the data transfer requested by the DMA transfer command.

公开(公告)号：US20210049030A1

公开(公告)日：2021-02-18

申请号：US16542777

申请日：2019-08-16

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Louis REGNIERE ,  Anthony ASARO ,  Jeffrey G. CHENG

IPC: G06F9/455

Abstract: The present disclosure relates to techniques for allocating performance counters to virtual functions in response to a request from a respective one of the virtual functions. In response to receiving a request from a respective one of the virtual functions for a performance counter, a security processor is configured to allocate, via a controller, a register associated with a processor to the virtual function, such that the register is configured to implement the performance counter.

公开(公告)号：US20150363310A1

公开(公告)日：2015-12-17

申请号：US14833850

申请日：2015-08-24

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Anthony ASARO ,  Kevin NORMOYLE ,  Mark HUMMEL

IPC: G06F12/02

CPC classification number: G06F12/1036 ,  G06F12/0284 ,  G06F12/0646 ,  G06F12/08 ,  G06F12/10 ,  G06F12/109 ,  G06F2212/1012 ,  G06F2212/152 ,  G06F2212/656 ,  G06F2212/657

Abstract: A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a first processor configured for unified operation with a second processor. The method includes receiving a memory operation from a processor and mapping the memory operation to one of a plurality of memory heaps. The mapping produces a mapping result. The method also includes providing the mapping result to the processor.

Abstract translation: 一种用于将计算机装置中的处理器执行的存储器操作分配给存储器的方法和系统，所述计算机装置具有配置成与第二处理器统一操作的第一处理器 该方法包括从处理器接收存储器操作并将存储器操作映射到多个存储器堆中的一个。 映射生成映射结果。 该方法还包括向处理器提供映射结果。