公开(公告)号：US07451074B2

公开(公告)日：2008-11-11

申请号：US10103349

申请日：2002-03-21

Applicant: Gauthier Barret ,  Jean-François Pollet ,  Francis Lamotte

Inventor： Gauthier Barret ,  Jean-François Pollet ,  Francis Lamotte

IPC: G06F9/455

CPC classification number: G06F11/261

Abstract: A method of emulation or functional testing of a first microprocessor in its functional environment including one or several peripherals and at least one internal bus of communication between this first microprocessor and its peripherals, from a second microprocessor, consisting of deactivating the first microprocessor, using the communication bus(es) to communicate between the two microprocessors and the peripheral(s), and activating the second microprocessor, wherein the first microprocessor communicates with the second microprocessor over a series link and wherein the second microprocessor is realized by a simulation model.

Abstract translation: 一种在其功能环境中的第一微处理器的仿真或功能测试的方法，包括一个或多个外围设备以及该第一微处理器及其外围设备之间的至少一个内部总线通信，第二微处理器由第二微处理器，使第 通信总线以在所述两个微处理器和所述外围设备之间进行通信，以及激活所述第二微处理器，其中所述第一微处理器通过串联链路与所述第二微处理器通信，并且其中所述第二微处理器由仿真模型实现。

公开(公告)号：US20080253162A1

公开(公告)日：2008-10-16

申请号：US12101266

申请日：2008-04-11

Applicant: Olivier Montfort ,  Sebastien Gaubert ,  Philippe Beliard

Inventor： Olivier Montfort ,  Sebastien Gaubert ,  Philippe Beliard

IPC: G11C17/00 ,  G11C7/00 ,  G11C8/00

CPC classification number: G11C11/5692 ,  G11C17/12 ,  G11C2211/5617

Abstract: The invention concerns a ROM comprising a set of memory points arranged in rows and columns, each memory point capable of storing two bits of data and comprising a single switch controllable to connect together first and second terminals of said switch, each of said first and second terminals being connected to one of first, second and third conductive lines, wherein said switch is connected via said first and second terminals between said first and second lines to encode a first data value, between said first and third lines to encode a second data value, between said second and third lines to encode a third data value, and both of said first and second terminals being connected to the same one of said first, second and third lines to encode a fourth data value.

Abstract translation: 本发明涉及一种ROM，其包括以行和列排列的一组存储器点，每个存储点能够存储两位数据，并且包括可控制以将所述开关的第一和第二端子连接在一起的单个开关，所述第一和第二 端子连接到第一，第二和第三导线之一，其中所述开关经由所述第一和第二端子在所述第一和第二线之间连接，以在所述第一和第三线之间编码第一数据值，以对第二数据值进行编码 ，在所述第二和第三行之间编码第三数据值，并且所述第一和第二终端都被连接到所述第一，第二和第三行中的相同的一个，以对第四数据值进行编码。

公开(公告)号：US07369071B2

公开(公告)日：2008-05-06

申请号：US11506452

申请日：2006-08-18

Applicant: Jean-François Pollet ,  Guillaume Cogniard

Inventor： Jean-François Pollet ,  Guillaume Cogniard

IPC: H03M1/00

CPC classification number: H04H60/04 ,  G10H1/361

Abstract: A mixer receiving a first analog signal and a first digital signal, corresponding to a succession, at a first frequency, of first messages each comprising a first number of bits, and providing a second analog signal, comprises an analog-to-digital converter of the first analog signal into a second digital signal, corresponding to a succession, at a second frequency greater than the first one, of second messages having a second number of bits smaller than the first one; a digital-to-digital converter of the second digital signal into a third one corresponding to a succession, at the second frequency, of third messages having the first number of bits; an interpolation unit providing a fourth digital signal corresponding to a succession, at the second frequency, of fourth messages having the first number of bits; an adder providing the sum of the third and fourth digital signals; and an output digital-to-analog converter.

Abstract translation: 接收第一模拟信号和第一数字信号的第一模拟信号和第一数字信号，所述第一模拟信号和第一数字信号在第一频率处对应于包括第一数量位的第一消息并提供第二模拟信号的第一信号，包括模数转换器 第一模拟信号转换成第二数字信号，对应于具有小于第一数量的第二数量位的第二消息的大于第一信号的第二频率的连续; 将所述第二数字信号的数/数转换器转换成具有所述第一位数的第三消息的第二频率的继续的第三数字转换器; 内插单元，以第二频率提供与具有第一比特数的第四个消息相对应的第四数字信号; 提供第三和第四数字信号之和的加法器; 和一个输出数模转换器。

公开(公告)号：US07283078B2

公开(公告)日：2007-10-16

申请号：US11446829

申请日：2006-06-05

Applicant: Frédéric Poulet ,  Guillaume Cogniard

Inventor： Frédéric Poulet ,  Guillaume Cogniard

IPC: H03M1/82

CPC classification number: H03M3/358 ,  H03M3/506 ,  H03M7/3024 ,  H03M7/3035 ,  H03M7/3037

Abstract: A converter of a digital signal into a pulse-width modulated signal, comprising a first conversion unit receiving, at a first frequency, successive digital signals each having one of a first determined number of values, and providing first intermediary signals, at the first frequency, each having one of a second determined number of values smaller than the first determined number; a unit performing a decimation of the first intermediary signals to provide second intermediary signals at a second frequency equal to the first frequency divided by the second determined number minus one; and a second conversion unit providing at the second frequency, from the second intermediary signals, a two-state pulse-width modulated signal having a minimum duration in one of the two states which is equal to the inverse of the first frequency, the first conversion unit receiving the pulse-width modulated signal.

Abstract translation: 将数字信号的转换器转换成脉冲宽度调制信号，包括第一转换单元，以第一频率接收每个具有第一确定数目的值之一的连续数字信号，并以第一频率提供第一中间信号 ，每个具有小于所述第一确定数量的第二确定数量的值中的一个; 执行对第一中间信号的抽取以使第二中间信号以等于第二确定数减去一的第一频率的第二频率的单元执行; 以及第二转换单元，从第二中间信号以第二频率提供具有等于第一频率的倒数的两个状态中的一个中的最小持续时间的两状态脉宽调制信号，第一转换 接收脉冲宽度调制信号的单元。

公开(公告)号：US10223290B2

公开(公告)日：2019-03-05

申请号：US15425877

申请日：2017-02-06

Applicant: DOLPHIN INTEGRATION

Inventor： Gilles Depeyrot ,  Olivier Monfort

IPC: G06F12/14 ,  G06F9/38

Abstract: The present invention concerns a method of protecting sensitive data, and a corresponding computing system processing device, comprising: entering, by a processing device, a sensitive date access mode in-which sensitive data is accessible; restricting, by a program running in the sensitive data access mode, one or more accessible address ranges for a non-secure function, and calling, from the sensitive data access mode, the non-secure function; and entering, by the processing device, a further operating mode to execute the non-secure function during which the processing device has access to only the one or more accessible address ranges.

公开(公告)号：US20140184318A1

公开(公告)日：2014-07-03

申请号：US14141369

申请日：2013-12-26

Applicant: Dolphin Integration

Inventor： Loïc Sibeud ,  Grégoire Gimenez

IPC: G05F1/46

CPC classification number: G05F1/468 ,  H03K19/0016

Abstract: The invention concerns power supply circuitry for controlling a power-up phase of an islet of an integrated circuit, the circuitry having: a switch (102) controlled by a current and coupled between a supply voltage rail (104) and an internal voltage rail (105) of the islet.

Abstract translation: 本发明涉及用于控制集成电路的小岛的上电阶段的电源电路，该电路具有：由电流控制并耦合在电源电压轨道（104）和内部电压轨道（104）之间的开关（102） 105）的小岛。

公开(公告)号：US20140104936A1

公开(公告)日：2014-04-17

申请号：US14051357

申请日：2013-10-10

Applicant: DOLPHIN INTEGRATION

Inventor： Ilan Sever

IPC: G11C11/412 ,  G11C29/08

CPC classification number: G11C11/412 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/22 ,  G11C11/418 ,  G11C11/419 ,  G11C29/08

Abstract: The invention concerns a memory array having memory cells arranged in columns and rows, the memory cells of each column being coupled to at least one common write line of their column, the memory cells of each row being coupled to a common selection line of their row, wherein each of the memory cells includes a latch formed of a pair of inverters cross-coupled between first and second storage nodes; a first transistor coupled between the first storage node and a first test data input; and a second transistor coupled between the second storage node and a second test data input.

Abstract translation: 本发明涉及具有以列和行排列的存储单元的存储器阵列，每列的存储单元耦合到其列的至少一个公共写入线，每行的存储单元耦合到其行的公共选择行 其中每个存储单元包括由在第一和第二存储节点之间交叉耦合的一对反相器形成的锁存器; 耦合在第一存储节点和第一测试数据输入之间的第一晶体管; 以及耦合在所述第二存储节点和第二测试数据输入之间的第二晶体管。

公开(公告)号：US08555227B2

公开(公告)日：2013-10-08

申请号：US13197930

申请日：2011-08-04

Applicant: Yahia Mallem ,  Mickael Giroud ,  Lionel Jure

Inventor： Yahia Mallem ,  Mickael Giroud ,  Lionel Jure

IPC: G06F17/50

CPC classification number: G06F1/10

Abstract: The invention concerns a computer implemented method of circuit conception of a clock tree (200) comprising: a plurality of pulse generators (202) each being coupled to the input of one or more pulsed latches and being arranged to generate a pulsed signal (PS); and a tree of buffers (204) for supplying a clock signal (CLK) to the pulse generators, the method comprising: the conception of the clock tree without pulse generators based on a timing analysis by the computer of the propagation of clock edges in the clock tree; and replacing by the computer in the clock tree at least one buffer, coupled to the input of each pulsed latch, by a pulse generator.

Abstract translation: 本发明涉及一种计算机实现的时钟树（200）的电路概念的方法，包括：多个脉冲发生器（202），每个脉冲发生器（202）耦合到一个或多个脉冲锁存器的输入端，并被布置成产生脉冲信号（PS） ; 以及用于向脉冲发生器提供时钟信号（CLK）的缓冲器树（204），所述方法包括：基于由计算机对时钟沿的传播的脉冲发生器的时钟树的构思 时钟树 并且由时钟树中的计算机替换由脉冲发生器耦合到每个脉冲锁存器的输入的至少一个缓冲器。

公开(公告)号：US20120032721A1

公开(公告)日：2012-02-09

申请号：US13197930

申请日：2011-08-04

Applicant: Yahia MALLEM ,  Mickael GIROUD ,  Lionel JURE

Inventor： Yahia MALLEM ,  Mickael GIROUD ,  Lionel JURE

IPC: G06F1/04 ,  H05K13/00 ,  G06F17/50

CPC classification number: G06F1/10

Abstract: The invention concerns a computer implemented method of circuit conception of a clock tree (200) comprising: a plurality of pulse generators (202) each being coupled to the input of one or more pulsed latches and being arranged to generate a pulsed signal (PS); and a tree of buffers (204) for supplying a clock signal (CLK) to the pulse generators, the method comprising: the conception of the clock tree without pulse generators based on a timing analysis by the computer of the propagation of clock edges in the clock tree; and replacing by the computer in the clock tree at least one buffer, coupled to the input of each pulsed latch, by a pulse generator.

Abstract translation: 本发明涉及一种计算机实现的时钟树（200）的电路概念的方法，包括：多个脉冲发生器（202），每个脉冲发生器（202）耦合到一个或多个脉冲锁存器的输入端，并被布置成产生脉冲信号（PS） ; 以及用于向脉冲发生器提供时钟信号（CLK）的缓冲器树（204），所述方法包括：基于由计算机对时钟沿的传播的脉冲发生器的时钟树的构思 时钟树 并且由时钟树中的计算机替换由脉冲发生器耦合到每个脉冲锁存器的输入的至少一个缓冲器。

公开(公告)号：US20100244911A1

公开(公告)日：2010-09-30

申请号：US12728796

申请日：2010-03-22

Applicant: Romuald Soileux ,  Sébastien Gaubert

Inventor： Romuald Soileux ,  Sébastien Gaubert

IPC: H03L7/00

CPC classification number: H03K17/223 ,  H03K19/0016

Abstract: The invention concerns a supply circuitry system and method, including a supply circuitry arranged to control a power-up phase at the end of a sleep period of a circuit region of an integrated circuit, the supply circuitry comprising: first and second switches coupled between a supply rail and a supply node of the circuit region, the supply rail being coupled to receive a supply voltage (VDD) from a power supply unit; a comparator arranged to provide an output based on a comparison between a voltage at the supply node (VDD_INT) and a reference voltage (VREF); and control circuitry coupled to control terminals of the first and second switches and arranged to activate the first switch at the start of the power-up phase, and to activate the second switch once the output of the comparator indicates that the voltage at the supply node is greater than the reference voltage.

Abstract translation: 本发明涉及一种供电电路系统和方法，其包括供电电路，该供电电路设置成在集成电路的电路区域的睡眠周期结束时控制加电阶段，该电源电路包括：第一和第二开关， 供电轨和电路区的供电节点，供电轨被耦合以从电源单元接收电源电压（VDD）; 比较器，被布置为基于供电节点处的电压（VDD_INT）和参考电压（VREF）之间的比较来提供输出; 以及控制电路，其耦合到第一和第二开关的控制端子，并被布置成在上电阶段开始时激活第一开关，并且一旦比较器的输出指示电源节点处的电压，则激活第二开关 大于参考电压。