Abstract:
At a receiver incoming coded OFDM Symbol Data are passed through a Coarse Symbol Timing Synchronization module to determine the approximate start of the symbol. In one embodiment this is accomplished through correlation. The symbol is then passed through an FFT (2K or 8K, depending on the mode desired by the receiver). Since the Coarse Symbol Timing Synchronization module only determines an approximate start point of the symbol, a process of fine synchronization is used to adjust this approximate start point and determine a more accurate start point of the symbol. In this manner, the receiver is enabled to process COFDM symbols in DVB-T transmissions (where the symbols include a cyclic prefix to overcome echoes). One output of an FFT operation is magnitude. Magnitude is used for Channel Estimation (or Channel Correction). Another output of an FFT operation is phase discontinuity or rotations. Phase discontinuities are used in a fine synchronization process to determine the number of phase discontinuities. Phase discontinuity data of the symbol is passed through an N-Point FFT.
Abstract:
Systems and methods for creating virtual stop-off points in a movie title, where the viewer can explore interesting content using zoom, pan and gamma controls are provided. Methods include creating an interest point from one or more digital video titles. Systems include a composer for creating interest points in a video and a viewer for manipulating and displaying the interest points.
Abstract:
Methods and apparatus, including computer program products, implementing and using techniques for computing motion vectors in a digital video sequence are disclosed. A recursive hierarchical method is used to determine a motion vector by using multiple resolution levels of the image frames. A best motion vector is first determined for the lowest resolution level. The best motion vector is propagated to a higher resolution level, where some adjustments are made and a new best motion vector is determined. The new best motion vector is propagated to yet another higher resolution level, where more adjustments are made and another new best motion vector is determined. This process is repeated until the highest, original, resolution level has been reached and a best motion vector has been identified. The identified best motion vector at the original resolution level is used for performing motion compensation.
Abstract:
An interlaced television signal is derived from an interlaced 625 line, nominally 50 Hz field rate television signal, the derived television signal having perceived reduced line structure and reduce flicker. The field rate and the number of lines of the derived television signal are increased with respect to the field rate and the number of lines of the original television signal, such that perceived flicker and line structure in the derived television signal is reduced. The increase in the field rate and the increase in the number of lines in the derived television signal results in a horizontal scanning rate that does not substantially exceed twice the horizontal scanning rate of the original television signal while minimizing undesirable motion artifacts.
Abstract:
The invention provides for automatically identifying the location of a displayed video window based upon a characterization of selected portions of the image for realness based upon a distribution of luminance values for the selected portions. The image is then searched mathematically for a large rectangle of realness, and if found, a similar operation is performed in a smaller rectangle around each of the edges of the large rectangle, in turn, zooming in to a resolution of one pixel, thus identifying the position of the edge. This process can be repeated as often as necessary in order to maintain a fix on the edges of the video window.
Abstract:
A packet based high bandwidth copy protection method is described that includes the following operations. Forming a number of data packets at a source device, encrypting selected ones of the data packets based upon a set of encryption values, transmitting the encrypted data packets from the source device to a sink device coupled thereto, decrypting the encrypted data packets based in part upon the encryption values, and accessing the decrypted data packets by the sink device.
Abstract:
A decoding system decodes forward error correction (FEC) encoded data. Factor graph circuitry (such as trellis decoder circuitry) processes the FEC encoded data according to at least one factor graph. Order restoring circuitry (such as convolutional deinterleaver circuitry) is coupled to an output of the factor graph circuitry and restores ordering of symbols in the encoded data. Error detection and correction circuitry is coupled to an output of the order restoring circuitry and processes block-based error correcting codes to detect and correct errors in the FEC encoded data and to provide a hard-decision output to an output of the decoding system. Feedback circuitry (such as convolutional interleaver circuitry and symbol interleaver circuitry) is coupled to process the hard-decision output from the error correction and detection circuitry and to provide the processed hard-decision output to the factor graph circuitry.
Abstract:
A video controller having a processor for processing executable instructions and associated data and a number of data ports, a method of acquiring extended display identification data (EDID) by a requesting one of the data ports is described. When on-board power supply is activated, an off-board power supply is deactivated and then the now active on-board power supply provides power to a memory device used to store the EDID and the executable instructions and associated data and to an on-board clock circuit capable of providing a high frequency clock signal. The on-board clock circuit, in turn, provides the high frequency clock signal from the on-board clock circuit to the memory device and if a memory read operation had been in progress when the on-board power supply was activated, then the memory read operation is completed.
Abstract:
An all-digital frequency conversion apparatus is provided that achieves frequency conversion using a simple phase detector and integer and fractional phase feedback information from a digital oscillator output. In an embodiment, a target phase accumulator unit generates a target phase signal to the phase detector unit. The target phase accumulator unit receives inputs from a reference signal input, and a target phase input value. The digital phase detector unit receives the reference signal, a current phase feedback input signal, and the target phase input signal. The phase detector unit outputs a frequency setting signal to a frequency value generator unit. The detector output is based on the difference between the current phase and the target phase. A frequency value generator unit is configured to output a frequency value signal to a digital oscillator unit that generates a corresponding digital output signal that is directly fed back to the current phase feedback input of the phase detector unit. A method, computing system, and software product that implement the present invention are also provided.
Abstract:
Detecting when the on-board power supply is powered on or off by an auto activity detection circuit by determining if the reference clock signal (TCLK) is toggling and if the reference clock signal is toggling, then charging a capacitor to a high voltage in the auto activity detection circuit based on the toggling reference clock signal, and outputting an on-board power supply activity signal based upon the high voltage by the auto activity detection circuit indicative of whether or not the on-board power supply is active