公开(公告)号：US09069602B2

公开(公告)日：2015-06-30

申请号：US14037214

申请日：2013-09-25

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark

IPC: G06F9/46 ,  G06F3/06

CPC classification number: G06F12/063 ,  G06F3/061 ,  G06F3/0656 ,  G06F3/0683 ,  G06F9/3004 ,  G06F9/3836 ,  G06F9/467 ,  G06F2212/251 ,  H04L45/74

Abstract: A transactional memory (TM) includes a control circuit pipeline and an associated memory unit. The memory unit stores a plurality of rings. The pipeline maintains, for each ring, a head pointer and a tail pointer. A ring operation stage of the pipeline maintains the pointers as values are put onto and are taken off the rings. A put command causes the TM to put a value into a ring, provided the ring is not full. A get command causes the TM to take a value off a ring, provided the ring is not empty. A put with low priority command causes the TM to put a value into a ring, provided the ring has at least a predetermined amount of free buffer space. A get from a set of rings command causes the TM to get a value from the highest priority non-empty ring (of a specified set of rings).

Abstract translation: 事务存储器（TM）包括控制电路管线和相关联的存储器单元。 存储单元存储多个环。 对于每个环，流水线保持头指针和尾指针。 管道的环操作阶段将维护指针，因为值被放置在环上并被取消。 如果环未满，则put命令会使TM将值放入环中。 如果环不为空，则get命令使TM取环， 如果环具有至少预定量的可用缓冲空间，则具有低优先级命令的put将导致TM将值放入环中。 从一组ring命令获取，使TM从最高优先级非空环（指定的一组环）获取一个值。

公开(公告)号：US08972668B2

公开(公告)日：2015-03-03

申请号：US13675309

申请日：2012-11-13

Applicant: Gavin J. Stark

Inventor： Gavin J. Stark

IPC: G06F12/00 ,  G06F9/46 ,  G06F9/34

CPC classification number: G06F13/287 ,  G06F7/10 ,  G06F9/34 ,  G06F9/467 ,  G06F12/00 ,  G06F13/00 ,  G06F13/4234 ,  G06F17/30 ,  Y02D10/14 ,  Y02D10/151

Abstract: A transactional memory (TM) receives a lookup command across a bus from a processor. The command includes a memory address, a starting bit position, and a mask size. In response to the command, the TM pulls an input value (IV). The memory address is used to read a word containing multiple result values (RVs) and multiple key values from memory. Each key value indicates a single RV to be output by the TM. A selecting circuit within the TM uses the starting bit position and mask size to select a portion of the IV. The portion of the IV is a key selector value. A key value is selected based upon the key selector value. A RV is selected based upon the key value. The key value is selected by a key selection circuit. The RV is selected by a result value selection circuit.

Abstract translation: 事务存储器（TM）从处理器接收总线上的查找命令。 该命令包括存储器地址，起始位位置和掩码大小。 响应该命令，TM拉动输入值（IV）。 存储器地址用于从存储器读取包含多个结果值（RV）和多个键值的单词。 每个键值表示TM输出的单个RV。 TM内的选择电路使用起始位位置和掩码大小来选择IV的一部分。 IV的部分是关键选择器值。 基于键选择器值选择键值。 基于键值选择RV。 键值由键选择电路选择。 RV由结果值选择电路选择。

公开(公告)号：US08972623B2

公开(公告)日：2015-03-03

申请号：US13875968

申请日：2013-05-02

Applicant: John Anthony Harper

Inventor： John Anthony Harper

IPC: G06F9/455

CPC classification number: G06F3/0653 ,  G06F3/0604 ,  G06F3/067 ,  G06F13/28 ,  H04L47/10 ,  H04L47/2441 ,  H04L47/621 ,  H04L47/6255

Abstract: A network appliance includes a first processor, a second processor, a first storage device, and a second storage device. A first status information is stored in the first storage device. The first processor is coupled to the first storage device. A queue of data is stored in the second storage device. The first status information indicates if traffic data stored in the queue of data is permitted to be transmitted. The second processor is coupled to the second storage device. The first processor communicates with the second processor. The traffic data includes packet information. The first storage device is a high speed memory only accessible to the first processor. The second storage device is a high capacity memory accessible to multiple processors. The first status information is a permitted bit that indicates if the traffic data within the queue of data is permitted to be transmitted.

Abstract translation: 网络设备包括第一处理器，第二处理器，第一存储设备和第二存储设备。 第一状态信息存储在第一存储装置中。 第一处理器耦合到第一存储设备。 数据队列存储在第二存储设备中。 第一状态信息指示是否允许发送存储在数据队列中的业务数据。 第二处理器耦合到第二存储设备。 第一处理器与第二处理器通信。 业务数据包括分组信息。 第一存储设备是只能由第一处理器访问的高速存储器。 第二存储设备是可由多个处理器访问的高容量存储器。 第一状态信息是指示允许发送数据队列内的业务数据的允许位。

公开(公告)号：US08930675B2

公开(公告)日：2015-01-06

申请号：US13675353

申请日：2012-11-13

Applicant: Gavin J. Stark

Inventor： Gavin J. Stark

IPC: G06F12/08 ,  G06F9/46 ,  G06F9/34

CPC classification number: G06F9/467 ,  G06F9/34 ,  G06F12/023 ,  G06F12/08 ,  G06F2212/251

Abstract: A transactional memory (TM) receives a lookup command across a bus from a processor. The command includes a memory address. In response to the command, the TM pulls an input value (IV). The memory address is used to read a word containing multiple result values (RVs), multiple reference values, and multiple mask values from memory. A selecting circuit within the TM uses a starting bit position and a mask size to select a portion of the IV. The portion of the IV is a lookup key value (LKV). The LKV is masked by each mask value thereby generating multiple masked values. Each masked value is compared to a reference value thereby generating multiple comparison values. A lookup table generates a selector value based upon the comparison values. A result value is selected based on the selector value. The selected result value is then communicated to the processor via the bus.

Abstract translation: 事务存储器（TM）从处理器接收总线上的查找命令。 该命令包括一个内存地址。 响应该命令，TM拉动输入值（IV）。 存储器地址用于从存储器读取包含多个结果值（RV），多个参考值和多个掩码值的单词。 TM内的选择电路使用起始位位置和掩码大小来选择IV的一部分。 IV的部分是查询键值（LKV）。 每个掩码值屏蔽LKV，从而产生多个掩蔽值。 将每个屏蔽值与参考值进行比较，从而生成多个比较值。 查找表根据比较值生成选择器值。 根据选择器值选择结果值。 所选择的结果值然后经由总线传送到处理器。

公开(公告)号：US08929374B2

公开(公告)日：2015-01-06

申请号：US13337184

申请日：2011-12-26

Applicant: Johann Heinrich Tönsing ,  Roelof Nico DuToit ,  Gysbert Floris van Beek Van Leeuwen ,  Jan Niel Viljoen ,  David Wells ,  Leon Johannes Brits ,  Jan Christoffel DuToit

Inventor： Johann Heinrich Tönsing ,  Roelof Nico DuToit ,  Gysbert Floris van Beek Van Leeuwen ,  Jan Niel Viljoen ,  David Wells ,  Leon Johannes Brits ,  Jan Christoffel DuToit

IPC: H04L12/28 ,  H04L12/56 ,  H04L12/701 ,  H04L12/935 ,  H04L29/06 ,  H04L12/54 ,  H04L12/741

CPC classification number: H04L47/12 ,  H04L12/5602 ,  H04L29/06095 ,  H04L29/0653 ,  H04L29/06591 ,  H04L45/00 ,  H04L45/74 ,  H04L47/20 ,  H04L47/2483 ,  H04L47/41 ,  H04L49/3009 ,  H04L49/309

Abstract: A system and method for handling a digital electronic flow between a first and second entity in which a flow policy is determined that is to be applied to the flow and the flow is then directed along a path in accordance with the policy. An ID is supplied for each flow and a tag associated with each flow which indicates the policy to be applied to its associated flow. Flows are also associated with one another, with associated flows having associated policies. In particular the flow may be processed or forwarded. The path may include a graph structure and virtual applications.

Abstract translation: 一种用于处理第一和第二实体之间的数字电子流的系统和方法，其中确定要应用于流的流策略和流，然后根据策略沿着路径被引导。 为每个流提供ID，并且与每个流相关联的标签指示要应用于其关联流的策略。 流也相互关联，相关联的流具有相关联的策略。 特别地，流程可以被处理或转发。 该路径可以包括图形结构和虚拟应用。

公开(公告)号：US08908693B2

公开(公告)日：2014-12-09

申请号：US13690195

申请日：2012-11-30

Applicant: Rolf Neugebauer ,  Gavin J. Stark ,  Espen Skoglund

Inventor： Rolf Neugebauer ,  Gavin J. Stark ,  Espen Skoglund

IPC: H04L12/56 ,  H04L12/743

CPC classification number: H04L47/18 ,  H04L45/7453 ,  H04L45/7457 ,  H04L47/32 ,  H04L47/34

Abstract: A flow key is determined from an incoming packet. Two hash values A and B are then generated from the flow key. Hash value A is an index into a hash table to identify a hash bucket. Multiple simultaneous CAM lookup operations are performed on fields of the bucket to determine which ones of the fields store hash value B. For each populated field there is a corresponding entry in a key table and in other tables. The key table entry corresponding to each field that stores hash value B is checked to determine if that key table entry stores the original flow key. When the key table entry that stores the original flow key is identified, then the corresponding entries in the other tables are determined to be a “lookup output information value”. This value indicates how the packet is to be handled/forwarded by the network appliance.

Abstract translation: 从输入包确定流密钥。 然后从流密钥生成两个散列值A和B. 哈希值A是哈希表中用于标识哈希桶的索引。 在桶的字段上执行多个同时的CAM查找操作，以确定哪些字段存储散列值B.对于每个填充字段，在键表和其他表中都有相应的条目。 检查对应于存储散列值B的每个字段的密钥表条目，以确定该密钥表条目是否存储原始流密钥。 当存储原始流密钥的密钥表条目被识别时，其他表中的相应条目被确定为“查找输出信息值”。 该值指示如何由网络设备处理/转发数据包。

公开(公告)号：US09069603B2

公开(公告)日：2015-06-30

申请号：US14287012

申请日：2014-05-24

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark

IPC: G06F3/00 ,  G06F13/00 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F9/46 ,  G06F13/16

CPC classification number: G06F9/467 ,  G06F12/00 ,  G06F13/1615 ,  G06F13/287 ,  G06F13/4022 ,  G06F13/4234 ,  H04L45/745 ,  Y02D10/14 ,  Y02D10/151

Abstract: A transactional memory (TM) receives an Atomic Metering Command (AMC) across a bus from a processor. The command includes a memory address and a meter pair indicator value. In response to the AMC, the TM pulls an input value (IV). The TM uses the memory address to read a word including multiple credit values from a memory unit. Circuitry within the TM selects a pair of credit values, subtracts the IV from each of the pair of credit values thereby generating a pair of decremented credit values, compares the pair of decremented credit values with a threshold value, respectively, thereby generating a pair of indicator values, performs a lookup based upon the pair of indicator values and the meter pair indicator value, and outputs a selector value and a result value that represents a meter color. The selector value determines the credit values written back to the memory unit.

Abstract translation: 事务存储器（TM）从处理器接收总线上的原子计量命令（AMC）。 该命令包括存储器地址和仪表对指示器值。 对于AMC，TM提取输入值（IV）。 TM使用存储器地址从存储器单元读取包括多个信用值的单词。 TM内的电路选择一对信用值，从该对信用值中的每一个中减去IV，从而生成一对递减的信用值，将一对递减的信用值与阈值进行比较，从而产生一对 指示符值，根据指示符值对和仪表对指示符值执行查找，并输出选择器值和表示仪表颜色的结果值。 选择器值确定写入存储单元的信用值。

公开(公告)号：US09069558B2

公开(公告)日：2015-06-30

申请号：US13552619

申请日：2012-07-18

Applicant: Gavin J. Stark

Inventor： Gavin J. Stark

IPC: G06F12/00 ,  G06F9/34 ,  G06F13/40

CPC classification number: G06F13/1615 ,  G06F9/3004 ,  G06F9/34 ,  G06F9/35 ,  G06F9/467 ,  G06F13/1663 ,  G06F13/40

Abstract: A lookup engine of a transactional memory (TM) has multiple hardware lookup structures, each usable to perform a different type of lookup. In response to a lookup command, the lookup engine reads a first block of first information from a memory unit. The first information configures the lookup engine to perform a first type of lookup, thereby identifying a first result value. If the first result value is not a final result value, then the lookup engine uses address information in the first result value to read a second block of second information. The second information configures the lookup engine to perform a second type of lookup, thereby identifying a second result value. This process repeats until a final result value is obtained. The type of lookup performed is determined by the result value of the preceding lookup and/or type information of the block of information for the next lookup.

Abstract translation: 事务存储器（TM）的查找引擎具有多个硬件查找结构，每个硬件查找结构可用于执行不同类型的查找。 响应于查找命令，查找引擎从存储器单元读取第一信息块。 第一信息配置查找引擎执行第一类型的查找，从而识别第一结果值。 如果第一结果值不是最终结果值，则查找引擎使用第一结果值中的地址信息来读取第二信息块。 第二信息配置查找引擎执行第二类型的查找，从而识别第二结果值。 该过程重复，直到获得最终结果值。 执行的查找类型由下一次查找的信息块的前一查找和/或类型信息的结果值确定。

公开(公告)号：US08930872B2

公开(公告)日：2015-01-06

申请号：US13399433

申请日：2012-02-17

Applicant: Gavin J. Stark

Inventor： Gavin J. Stark

IPC: G06F17/50 ,  H04L12/00 ,  G06F13/00

CPC classification number: G06F13/4022 ,  G06F13/00 ,  G06F13/28 ,  G06F17/5072 ,  G06F17/5077 ,  H04L12/54 ,  H04L12/56 ,  H04L51/00

Abstract: An island-based network flow processor (IB-NFP) integrated circuit includes rectangular islands disposed in rows. In one example, the configurable mesh data bus is configurable to form a command/push/pull data bus over which multiple transactions can occur simultaneously on different parts of the integrated circuit. The rectangular islands of one row are oriented in staggered relation with respect to the rectangular islands of the next row. The left and right edges of islands in a row align with left and right edges of islands two rows down in the row structure. The data bus involves multiple meshes. In each mesh, the island has a centrally located crossbar switch and six radiating half links, and half links down to functional circuitry of the island. The staggered orientation of the islands, and the structure of the half links, allows half links of adjacent islands to align with one another.

Abstract translation: 基于岛屿的网络流处理器（IB-NFP）集成电路包括以行排列的矩形岛。 在一个示例中，可配置的网格数据总线可配置成形成命令/推/拉数据总线，多个事务可以同时发生在集成电路的不同部分上。 一行的矩形岛相对于下一行的矩形岛定向成交错关系。 一行中的岛的左边缘和右边缘与行结构中两行向下的岛的左边缘和右边缘对齐。 数据总线涉及多个网格。 在每个网格中，岛具有位于中心的交叉开关和六个辐射半连接，并且一半连接到岛的功能电路。 岛屿的交错取向和半连接的结构允许相邻岛屿的一半链接彼此对齐。

公开(公告)号：US08930639B2

公开(公告)日：2015-01-06

申请号：US13675394

申请日：2012-11-13

Applicant: Gavin J. Stark

Inventor： Gavin J. Stark

IPC: G06F12/00 ,  G06F9/46 ,  G06F9/34

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0673 ,  G06F9/34 ,  G06F9/467 ,  G06F12/00 ,  G06F17/30386

Abstract: A transactional memory (TM) receives a lookup command across a bus from a processor. The command includes a memory address. In response to the command, the TM pulls an input value (IV). The memory address is used to read a word containing multiple result values (RVs), multiple reference values, and multiple prefix values from memory. A selecting circuit within the TM uses a starting bit position and a mask size to select a portion of the IV. The portion of the IV is a lookup key value (LKV). Mask values are generated based on the prefix values. The LKV is masked by each mask value thereby generating multiple masked values that are compared to the reference values. Based on the comparison a lookup table generates a selector value that is used to select a result value. The selected result value is then communicated to the processor via the bus.

Abstract translation: 事务存储器（TM）从处理器接收总线上的查找命令。 该命令包括一个内存地址。 响应该命令，TM拉动输入值（IV）。 存储器地址用于从存储器读取包含多个结果值（RV），多个引用值和多个前缀值的单词。 TM内的选择电路使用起始位位置和掩码大小来选择IV的一部分。 IV的部分是查询键值（LKV）。 基于前缀值生成掩码值。 LKV由每个掩码值屏蔽，从而产生与参考值进行比较的多个掩蔽值。 基于比较，查找表生成用于选择结果值的选择器值。 所选择的结果值然后经由总线传送到处理器。