公开(公告)号：US07531438B2

公开(公告)日：2009-05-12

申请号：US11491137

申请日：2006-07-24

申请人： Jih-Wen Chou ,  Chih-Hsun Chu ,  Hsiu-Chuan Shu

发明人： Jih-Wen Chou ,  Chih-Hsun Chu ,  Hsiu-Chuan Shu

IPC分类号： H01L21/3205

CPC分类号： H01L21/26586 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/66621 ,  H01L29/78 ,  Y10S438/981

摘要： A method of fabricating a recess channel transistor is provided. First, a hard mask is formed on a doped-semiconductor layer and a substrate. The doped-semiconductor layer and the substrate are etched to form a trench and define a source/drain in the doped-semiconductor layer. An implantation process is performed with a tilt angle on sidewalls of the trench to form an implant area. A thermal oxidation process is performed to form an oxide layer. The oxide layer comprises a first thickness on the source/drain in the sidewalls of the trench and a second thickness on the other portion in the sidewalls of the trench.

摘要翻译： 提供一种制造凹槽通道晶体管的方法。 首先，在掺杂半导体层和基板上形成硬掩模。 蚀刻掺杂半导体层和衬底以形成沟槽并且在掺杂半导体层中限定源极/漏极。 在沟槽的侧壁上以倾斜角度执行植入工艺以形成植入区域。 进行热氧化处理以形成氧化物层。 氧化物层包括在沟槽的侧壁中的源极/漏极上的第一厚度和在沟槽的侧壁中的另一部分上的第二厚度。

公开(公告)号：US20080308899A1

公开(公告)日：2008-12-18

申请号：US11763566

申请日：2007-06-15

申请人： Yu-Lien Huang ,  Yi-Chen Huang ,  Jim Cy Huang ,  Weng Chang ,  Hun-Jan Tao

发明人： Yu-Lien Huang ,  Yi-Chen Huang ,  Jim Cy Huang ,  Weng Chang ,  Hun-Jan Tao

IPC分类号： H01L29/06 ,  H01L29/00

CPC分类号： H01L21/823425 ,  H01L21/823468 ,  Y10S438/981

摘要： Provided is a semiconductor device including a substrate. A gate formed on the substrate. The gate includes a sidewall. A spacer formed on the substrate and adjacent the sidewall of the gate. The spacer has a substantially triangular geometry. A contact etch stop layer (CESL) is formed on the first gate and the first spacer. The thickness of the CESL to the width of the first spacer is between approximately 0.625 and 16.

摘要翻译： 提供了包括基板的半导体器件。 形成在基板上的栅极。 门包括侧壁。 在衬底上形成并且邻近门的侧壁的间隔物。 间隔件具有基本上三角形的几何形状。 在第一栅极和第一间隔物上形成接触蚀刻停止层（CESL）。 CESL的厚度与第一间隔件的宽度在大约0.625和16之间。

公开(公告)号：US07348247B2

公开(公告)日：2008-03-25

申请号：US10981987

申请日：2004-11-05

申请人： Geon-Ook Park

发明人： Geon-Ook Park

IPC分类号： H01L21/336

CPC分类号： H01L29/78 ,  H01L29/42368 ,  Y10S148/163 ,  Y10S438/981

摘要： Semiconductor devices and methods of manufacturing the same are disclosed. A disclosed semiconductor device comprises a semiconductor substrate; a gate formed on the semiconductor substrate; a gate oxide layer interposed between the semiconductor substrate and the gate; and source and drain regions formed within the substrate at opposite sides of the gate. The gate oxide layer has a first region with a first thickness and a second region with a second thickness. The second thickness is thicker than the first thickness.

公开(公告)号：US20070243676A1

公开(公告)日：2007-10-18

申请号：US11379057

申请日：2006-04-18

申请人： Jhy-Jyi Sze

发明人： Jhy-Jyi Sze

IPC分类号： H01L21/8234

CPC分类号： H01L27/14643 ,  H01L27/14609 ,  H01L27/1463 ,  H01L27/14689 ,  Y10S438/981

摘要： A semiconductor substrate is provided on which a plurality of shallow trench isolations (STI) defining a plurality of active areas are formed. The active areas comprise a photo sensing region, and a plurality of photodiodes are formed in each photo sensing region. Then a local oxidation of silicon isolation (LOCOS) layer is formed by performing a LOCOS process. Thereafter a plurality of gates are respectively formed in each active area, where the gates partially overlap the LOCOS layer. Finally doped regions are formed in the semiconductor substrate where the gate does not cover the LOCOS layer.

摘要翻译： 设置半导体衬底，在其上形成限定多个有源区的多个浅沟槽隔离（STI）。 有源区域包括光感测区域，并且在每个感光区域中形成多个光电二极管。 然后通过执行LOCOS工艺形成硅隔离（LOCOS）层的局部氧化。 此后，在每个有效区域中分别形成多个栅极，其中栅极与LOCOS层部分重叠。 最后掺杂区形成在半导体衬底中栅极不覆盖LOCOS层。

公开(公告)号：US07262103B2

公开(公告)日：2007-08-28

申请号：US10740136

申请日：2003-12-18

申请人： Joon Hyeon Lee ,  Woon Yong Kim

发明人： Joon Hyeon Lee ,  Woon Yong Kim

IPC分类号： H01L21/336

CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823462 ,  H01L29/6656 ,  Y10S438/954 ,  Y10S438/981

摘要： Disclosed is a method for forming salicide in a semiconductor device. The method comprises the steps of: forming a first and a second gate oxide film and in a non-salicide region and a salicide region, the first gate oxide film being thicker than the second gate oxide film; forming a conductive layer and a nitride based hard mask layer, and then selectively removing the conductive layer, the hard mask layer, the first gate oxide film, and the second gate oxide film, thereby forming gate electrodes and simultaneously exposing an active region of the salicide region; forming a spacer oxide film on an upper surface, except for the hard mask layer, of a second resultant structure; selectively removing the spacer oxide film, thereby forming a spacer and simultaneously exposing the active region of the salicide region; removing the hard mask layer; and forming a salicide film on the upper surfaces of the gate electrodes and on the surface of the active region in the salicide region. Therefore, a non-salicide region and a salicide region can be formed selectively and simultaneously in a one-chip semiconductor device, so that the number of steps for a salicide forming process can be reduced.

摘要翻译： 公开了一种在半导体器件中形成硅化物的方法。 该方法包括以下步骤：形成第一和第二栅极氧化膜，并且在非自对准硅化物区域和自对准硅化物区域中，所述第一栅极氧化物膜比所述第二栅极氧化物膜厚; 形成导电层和氮化物基硬掩模层，然后选择性地去除导电层，硬掩模层，第一栅极氧化膜和第二栅极氧化物膜，由此形成栅电极并同时曝光 自杀地区; 在除了硬掩模层之外的上表面上形成第二结构结构的间隔氧化膜; 选择性地去除间隔氧化膜，从而形成间隔物并同时暴露自对准区域的活性区域; 去除硬掩模层; 以及在所述栅电极的上表面和所述自对准区域中的有源区的表面上形成自对准硅膜。 因此，可以在单芯片半导体器件中选择性和同时地形成非自对准硅化物区域和自对准硅化物区域，从而可以减少用于硅化物形成工艺的步骤数量。

公开(公告)号：US07262102B2

公开(公告)日：2007-08-28

申请号：US11233569

申请日：2005-09-23

申请人： Graham R Wolstenholme ,  Mark A Helm

发明人： Graham R Wolstenholme ,  Mark A Helm

IPC分类号： H01L21/8239 ,  H01L21/762

CPC分类号： H01L27/10894 ,  H01L21/76224 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823857 ,  H01L21/823878 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10897 ,  Y10S438/981 ,  Y10T29/41 ,  Y10T29/5313

摘要： A dielectric layer (e.g., an interpoly dielectric layer) is deposited over low and high voltage devices of a peripheral memory device. The dielectric behaves as an oxidation and wet oxide etch barrier. The dielectric prevents the devices from being stripped by a wet oxide etch that can result in the exposure of the silicon corners. The exposure of a silicon corner may increase thinning of a gate oxide at the field edge. This causes variability and unreliability in the device. The dielectric is not removed from a device until the device is ready for processing. That is, the dielectric remains on a device until the growing of a gate oxide on that device has begun. This reduces the exposure of the silicon corner. Hedges that result may be removed by exposing a trench in the field oxide at the hedge.

公开(公告)号：US07242053B1

公开(公告)日：2007-07-10

申请号：US11036738

申请日：2005-01-14

申请人： Sunil D. Mehta ,  Kerry Ilgenstein

发明人： Sunil D. Mehta ,  Kerry Ilgenstein

IPC分类号： H01L29/788

CPC分类号： H01L27/105 ,  G11C16/30 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558 ,  Y10S438/981

摘要： In one embodiment, an EEPROM device having voltage limiting charge pumping circuitry includes charge-pumping circuitry that limits the voltage supplied to the high voltage transistors to levels below the breakdown field of the tunnel oxide layer. The EEPROM device includes a substrate having a programming region, a tunnel region, a sensing region, and a low voltage region. A first oxide layer having a first thickness overlies the tunnel region and the sensing region. A second oxide layer having a second thickness overlies the low voltage region. The first oxide thickness is greater than the second oxide thickness. A charge pumping circuit is coupled to the programming region and to the tunnel region. The charge pumping circuit impresses a voltage level across the first oxide layer that is below the field breakdown voltage of first oxide layer.

摘要翻译： 在一个实施例中，具有电压限制电荷泵浦电路的EEPROM器件包括电荷泵浦电路，其将提供给高压晶体管的电压限制在低于隧道氧化物层的击穿场的水平。 EEPROM器件包括具有编程区域，隧道区域，感测区域和低电压区域的衬底。 具有第一厚度的第一氧化物层覆盖隧道区域和感测区域。 具有第二厚度的第二氧化物层覆盖在低电压区域上。 第一氧化物厚度大于第二氧化物厚度。 电荷泵浦电路耦合到编程区域和隧道区域。 电荷泵浦电路使第一氧化物层的电压电平低于第一氧化物层的场击穿电压。

公开(公告)号：US20070148852A1

公开(公告)日：2007-06-28

申请号：US11616055

申请日：2006-12-26

申请人： Young Lee

发明人： Young Lee

IPC分类号： H01L21/8238

CPC分类号： H01L21/823857 ,  H01L21/823842 ,  Y10S438/981

摘要： A method of manufacturing a semiconductor device is provided. The method includes the steps of forming a gate oxide layer including an oxide layer containing a large amount of nitrogen on a semiconductor substrate on which an input/output (I/O) region including an NMOS region and a PMOS region are defined, forming a polysilicon on the gate oxide layer, selectively removing the polysilicon on the PMOS region, selectively removing the gate oxide layer on the PMOS region, forming a pure SiO2 layer on the semiconductor substrate of the PMOS region, removing a surface oxide layer on the remaining polysilicon generated when the pure SiO2 layer is formed, and forming a gate electrode polysilicon on the entire surface including the remaining polysilicon.

摘要翻译： 提供一种制造半导体器件的方法。 该方法包括以下步骤：在其上限定有包括NMOS区和PMOS区的输入/输出（I / O）区域的半导体衬底上形成包含含有大量氮的氧化物层的栅氧化层，形成 选择性地去除PMOS区上的多晶硅，选择性地去除PMOS区上的栅极氧化层，在PMOS区的半导体衬底上形成纯SiO 2层，去除 在形成纯SiO 2层时产生的剩余多晶硅上的表面氧化物层，并且在包括剩余多晶硅的整个表面上形成栅电极多晶硅。

公开(公告)号：US20070132041A1

公开(公告)日：2007-06-14

申请号：US11637705

申请日：2006-12-13

申请人： Chul Yoon

发明人： Chul Yoon

IPC分类号： H01L21/336 ,  H01L29/94

CPC分类号： H01L21/28238 ,  H01L21/022 ,  H01L21/0223 ,  H01L21/3144 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/11568 ,  H01L27/11573 ,  Y10S438/981

摘要： A method for forming gate dielectric layers having different thicknesses is provided, The method includes forming a lower oxide layer, a nitride layer, and an upper oxide layer on a semiconductor substrate; performing a first deglaze process to the semiconductor substrate keeping the lower oxide layer, the nitride layer, and the upper oxide layer in a first region, while removing the nitride layer and the upper oxide layer in second, third, and fourth regions; forming the first gate dielectric layer having a first thickness in the second, third, and fourth regions; performing a second deglaze process to the first gate dielectric layer in the third region, thereby forming a second gate dielectric layer having a second thickness; and performing a third deglaze process on the first gate dielectric layer on the fourth region, thereby forming a third gate dielectric layer having a third thickness.

摘要翻译： 提供一种形成具有不同厚度的栅介质层的方法。该方法包括在半导体衬底上形成低氧化层，氮化物层和上氧化物层; 在第二区域中去除氮化物层和上部氧化物层的同时，在第一区域内对保持低氧化物层，氮化物层和上部氧化物层的半导体衬底进行第一脱灰处理; 在所述第二，第三和第四区域中形成具有第一厚度的所述第一栅极介电层; 对所述第三区域中的所述第一栅极电介质层进行第二脱灰处理，从而形成具有第二厚度的第二栅极介电层; 以及对所述第四区域上的所述第一栅极电介质层进行第三脱灰处理，由此形成具有第三厚度的第三栅极电介质层。

公开(公告)号：US07224037B2

公开(公告)日：2007-05-29

申请号：US10894019

申请日：2004-07-20

申请人： Hideki Yasuoka ,  Masami Kouketsu ,  Susumu Ishida ,  Kazunari Saitou

发明人： Hideki Yasuoka ,  Masami Kouketsu ,  Susumu Ishida ,  Kazunari Saitou

IPC分类号： H01L27/092

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823892 ,  H01L27/0629 ,  H01L27/092 ,  Y10S438/981

摘要： Provided is a manufacturing method of a semiconductor integrated circuit device having a plurality of first MISFETs in a first region and a plurality of second MISFETs in a second region, which comprises forming a first insulating film between two adjacent regions of the first MISFET forming regions in the first region and the second MISFET forming regions in the second region; forming a second insulating film over the surface of the semiconductor substrate between the first insulating films in each of the first and second regions; depositing a third insulating film over the second insulating film; forming a first conductive film over the third insulating film in the second region; forming, after removal of the third and second insulating films from the first region, a fourth insulating film over the surface of the semiconductor substrate in the first region; and forming a second conductive film over the fourth insulating film; wherein the third insulating film remains over the first insulating film in the second region. The present invention makes it possible to raise the threshold voltage of a parasitic MOS and in addition, to suppress occurrence of an NBT phenomenon.

摘要翻译： 提供一种半导体集成电路器件的制造方法，该半导体集成电路器件在第一区域具有多个第一MISFET以及第二区域中的多个第二MISFET，其包括在第一MISFET形成区域的两个相邻区域之间形成第一绝缘膜， 在第二区域中的第一区域和第二MISFET形成区域; 在所述第一和第二区域中的每个中的所述第一绝缘膜之间的所述半导体衬底的表面上形成第二绝缘膜; 在所述第二绝缘膜上沉积第三绝缘膜; 在所述第二区域中在所述第三绝缘膜上形成第一导电膜; 在从所述第一区域去除所述第三绝缘膜和所述第二绝缘膜之后，在所述第一区域中的所述半导体衬底的表面上形成第四绝缘膜; 以及在所述第四绝缘膜上形成第二导电膜; 其中所述第三绝缘膜保留在所述第二区域中的所述第一绝缘膜上。 本发明使得可以提高寄生MOS的阈值电压，并且还抑制NBT现象的发生。