公开(公告)号：US06663454B2

公开(公告)日：2003-12-16

申请号：US09877496

申请日：2001-06-08

Applicant: Benjamin Edward Russ ,  Jack Barger

Inventor： Benjamin Edward Russ ,  Jack Barger

IPC: H01J900

CPC classification number: H01J29/028 ,  H01J9/185 ,  H01J29/467 ,  H01J2329/00

Abstract: A method of alignment of components of a field emission display comprising the steps of: attaching a first alignment barrier to a cathode substrate including electron emitters; positioning a gate frame against the first alignment barrier such that the gate frame is aligned with the cathode substrate; and sealing the gate frame in position against the first alignment barrier to the cathode substrate. The gate frame is a discrete component manufactured separately from the cathode substrate. A second alignment barrier is attached to the gate frame and an anode plate is positioned and sealed against the second alignment barrier such that the anode plate is aligned with the gate frame.

公开(公告)号：US06604970B1

公开(公告)日：2003-08-12

申请号：US09456285

申请日：1999-12-08

Applicant: Shuji Yamada

Inventor： Shuji Yamada

IPC: H01J900

CPC classification number: H01J29/04 ,  H01J1/316 ,  H01J9/027 ,  H01J29/028 ,  H01J2201/3165 ,  H01J2329/00 ,  H05K1/0289 ,  H05K3/4664

Abstract: A production method of an insulating layer includes a step of forming a first wire, a step of forming an insulating layer as a stack of M layers by repeatedly carrying out steps of laying and baking an insulating material on the first wire M times (M is an integer satisfying M≧3), and a step of forming a second wire on the insulating layer. An N-th insulating material used in formation of the N-th insulating layer (N is an integer satisfying 2≦N≦M−1) is baked at a temperature lower than a softening point of the N-th insulating material, and baking temperatures in formation of the (N+1)th to the M-th insulating layers are not more than the baking temperature in formation of the N-th insulating layer.

Abstract translation: 绝缘层的制造方法包括形成第一布线的步骤，通过重复地在第一布线M上铺设和烘烤绝缘材料的步骤，M层形成绝缘层作为叠层的步骤（M是 满足M> = 3的整数），以及在绝缘层上形成第二线的步骤。 用于形成第N绝缘层（N为满足2 <= N <= M-1的整数）的第N绝缘材料在低于第N绝缘材料的软化点的温度下被烘烤， 并且形成第（N + 1）个至第M绝缘层的烘烤温度不大于形成第N绝缘层时的烘烤温度。

公开(公告)号：US06592419B2

公开(公告)日：2003-07-15

申请号：US10032852

申请日：2001-10-22

Applicant: James J. Alwan

Inventor： James J. Alwan

IPC: H01J900

CPC classification number: H01J9/261 ,  H01J29/86

Abstract: A process for fabricating a flat panel display having a faceplate and a baseplate comprises creating an electric field between the faceplate and the baseplate to temporarily attract the faceplate to the baseplate and attaching the baseplate and faceplate to each other while the electric field is present. Capacitor(s) are formed on the faceplate and/or baseplate of a flat panel display such that a portion of the capacitor(s) is formed on the faceplate and is aligned with the pixel matrix and/or a portion of the capacitor(s) is formed on the baseplate and is aligned with the cathode member. The first and second portions of the capacitor(s) are energized to opposite polarity voltages, and an electric field is generated which attracts and aligns the two portions of the capacitor(s) to each other. When the two portions of the capacitor(s) are aligned and attracted to each other, the pixel matrix and cathode assembly are inherently aligned with each other. Once the faceplate and the baseplate are attached to each other, the capacitor(s) are de-energized and the electric field is dissipated.

公开(公告)号：US06579140B2

公开(公告)日：2003-06-17

申请号：US10200849

申请日：2002-07-22

Applicant: Ammar Derraa

Inventor： Ammar Derraa

IPC: H01J900

CPC classification number: H01J9/025

Abstract: A method for fabricating row lines and pixel openings of a field emission array that employs only two masks. A first mask is disposed over electrically conductive material and semiconductive material and includes apertures that are alignable between rows of pixels of the field emission array. Row lines of the field emission array are defined through the first mask. A passivation layer is then disposed over at least selected portions of the field emission array. A second mask, including apertures alignable over the pixel regions of the field emission array, is disposed over the passivation layer. The second mask is used in defining openings through the passivation layer and over the pixel regions of the field emission array. Conductive material exposed through the apertures of the second mask may also be removed to expose the underlying semiconductive grid and to further define the pixel openings.

公开(公告)号：US06506087B1

公开(公告)日：2003-01-14

申请号：US09301583

申请日：1999-04-29

Applicant: Masahiro Fushimi ,  Kunihiro Sakai

Inventor： Masahiro Fushimi ,  Kunihiro Sakai

IPC: H01J900

CPC classification number: H01J29/028 ,  H01J9/185 ,  H01J9/242 ,  H01J29/864 ,  H01J31/127 ,  H01J2201/3165 ,  H01J2329/864 ,  H01J2329/8645 ,  H01J2329/8655 ,  H01J2329/866 ,  Y10T225/12

Abstract: A method of manufacturing an image forming apparatus having an envelope made of members inclusive of a first substrate and a second substrate disposed at a space being set therebetween, image forming means and spacers disposed in the envelope, the spacers maintaining the space, the method comprising the steps of forming a spacer having a desired shape by cutting a spacer base member, and abutting the spacer upon the first and second substrates at non-cut surfaces of the spacer.

Abstract translation: 一种制造图像形成装置的方法，所述图像形成装置具有由包括第一基板的部件和设置在其间的空间的第二基板构成的封套，图像形成装置和设置在外壳中的间隔件，所述间隔件保持空间，所述方法包括 通过切割间隔件基件来形成具有期望形状的间隔件的步骤，并且在间隔件的非切割表面处将间隔件邻接在第一和第二基板上。

公开(公告)号：US06423239B1

公开(公告)日：2002-07-23

申请号：US09591192

申请日：2000-06-08

Applicant: David A. Cathey ,  Kevin Tjaden

Inventor： David A. Cathey ,  Kevin Tjaden

IPC: H01J900

CPC classification number: H01J9/025 ,  H01J2201/30403

Abstract: A method for fabricating sharp asperities. A substrate is provided which has a mask layer disposed thereon, and a layer of micro-spheres is disposed superjacent the mask layer. The micro-spheres are for patterning the mask layer. Portions of the mask layer are selectively removed, thereby forming circular masks. The substrate is isotropically etched, thereby creating sharp asperities.

Abstract translation: 一种制造尖锐凹凸的方法。 提供了具有设置在其上的掩模层的基板，并且在该掩模层的上方布置一层微球。 微球用于图案化掩模层。 选择性地去除掩模层的一部分，从而形成圆形掩模。 基板被各向同性地蚀刻，从而产生尖锐的凹凸。

公开(公告)号：US06312303B1

公开(公告)日：2001-11-06

申请号：US09356145

申请日：1999-07-19

Applicant: Zvi Yaniv ,  Richard Lee Fink

Inventor： Zvi Yaniv ,  Richard Lee Fink

IPC: H01J900

CPC classification number: B82Y10/00 ,  H01J9/025 ,  H01J2201/30469 ,  Y10S977/742 ,  Y10S977/753 ,  Y10S977/842 ,  Y10S977/888 ,  Y10S977/939

Abstract: Carbon nanotubes are aligned within a host phase of a material that has molecules that will align under a certain influence. When the host molecules become aligned, they cause the carbon nanotube fibers to also become aligned in the same direction. The film of aligned carbon nanotubes is then cured into a permanent phase, which can then be polished to produce a thin film of commonly aligned carbon nanotube fibers for use within a field emission device.

Abstract translation: 碳纳米管在具有将在一定影响下对准的分子的材料的主体相内对齐。 当主体分子变得对准时，它们使得碳纳米管纤维也在相同的方向上排列。 然后将对准的碳纳米管的膜固化成永久相，然后将其抛光以产生在场致发射器件内使用的共同排列的碳纳米管纤维的薄膜。

公开(公告)号：US06302756B1

公开(公告)日：2001-10-16

申请号：US09542335

申请日：2000-04-05

Applicant: Shigeyoshi Ootsuki ,  Shinichi Fukuzawa

Inventor： Shigeyoshi Ootsuki ,  Shinichi Fukuzawa

IPC: H01J900

CPC classification number: H01L27/3283 ,  H01L51/56

Abstract: The present invention provides a display device comprising anodes provided over a substrate, isolators provided on the anodes, an organic electroluminescence layer provided over the anodes and the isolators, and cathodes provided on the organic electroluminescence layer so that the cathodes are isolated from each other by the isolators.

Abstract translation: 本发明提供了一种显示装置，其包括设置在基板上的阳极，设置在阳极上的隔离器，设置在阳极和隔离体上的有机电致发光层，以及设置在有机电致发光层上的阴极，使得阴极彼此隔离， 隔离器。

公开(公告)号：US06220913B1

公开(公告)日：2001-04-24

申请号：US09247084

申请日：1999-02-09

Applicant: Yoshio Makita ,  Nobuhiko Takashima ,  Katsunosuke Ozawa ,  Tatsuo Yamaura ,  Satoshi Yoshikata ,  Masayuki Itakura

Inventor： Yoshio Makita ,  Nobuhiko Takashima ,  Katsunosuke Ozawa ,  Tatsuo Yamaura ,  Satoshi Yoshikata ,  Masayuki Itakura

IPC: H01J900

CPC classification number: H01J9/242 ,  H01J2329/8625

Abstract: An automatic support pillar transfer mechanism is provided that enables an enlarged transfer range, reduced produce failure and mass-production. The touch sensors 17a to 7c are arranged on the moving section 12 to measure the plane orientation of the surface of the jig 7. The jig adjusting section 6 is driven based on the measurement results on the plane orientations of surfaces of the jig 7 to adjust the surface of the jig 7 in parallel. With plural support pillars 15 sucked and held at predetermined intervals by the jig 7 adjusted in parallel, the bonding agent coated substrate 14 attached on the moving section 12 is descended to coat the bonding agent 13 onto the one ends of the support pillars 15. The substrate 16 to which the support pillars 15 are transferred is attached to the moving section 12. Variations in plane orientation of surfaces of the substrate 16 are respectively measured by means of the touch sensors 5a to 5c. The jig adjusting section 6 is driven according to the variations in plane orientation of the surfaces of the substrate 16. With the surface of the jig 7 arranged in parallel to the surface of the substrate 16, the moving section 12 is descended to transfer the support pillars 15 onto the surface of the substrate 16.

Abstract translation: 提供了一种自动支撑柱传送机构，其能够扩大传送范围，减少产品故障和批量生产。 触摸传感器17a〜7c配置在移动部12上，测定夹具7的表面的面取向。夹具调整部6基于夹具7的表面的面取向的测定结果进行驱动， 夹具7的表面平行。 通过平行调整的夹具7以预定的间隔吸附并保持多个支撑柱15，附着在移动部12上的粘合剂涂布基板14下降以将粘合剂13涂覆在支撑柱15的一端上。 支撑柱15被传送到的基板16被附接到移动部分12.基板16的表面的平面取向的变化分别通过触摸传感器5a至5c来测量。 根据基板16的表面的平面取向的变化来驱动夹具调整部6.随着夹具7的表面与基板16的表面平行地配置，移动部12下降以将支撑体 支柱15到基板16的表面上。

公开(公告)号：US06176752B1

公开(公告)日：2001-01-23

申请号：US09152772

申请日：1998-09-10

Applicant: Kevin Tjaden ,  David A. Cathey ,  John K. Lee

Inventor： Kevin Tjaden ,  David A. Cathey ,  John K. Lee

IPC: H01J900

CPC classification number: H01J9/025

Abstract: The present invention is a baseplate that has a supporting substrate with a primary surface upon which an array of emitters is formed. An insulator layer with a plurality of cavities aligned with respective emitters is disposed on the primary surface, and an extraction grid with a plurality of cavity openings aligned with respective emitters is deposited on the insulator layer. The extraction grid is made from a silicon based layer of material. A current control substrate formed from the silicon based layer of material of the extraction grid is provided such that the current control substrate is electrically isolated from the extraction grid and electrically connected to the emitters. The current control substrate has sufficient resistivity to limit the current from the emitters.