Control unit for data storage system and method for updating logical-to-physical mapping table

    公开(公告)号:US10545876B2

    公开(公告)日:2020-01-28

    申请号:US16180251

    申请日:2018-11-05

    Inventor: Che-Jen Su

    Abstract: A control unit for a data storage system is shown, which provides at least two buffers for updating mapping information through a host memory buffer HMB. A first buffer is provided for dynamic management of a physical-to-logical mapping table F2H that records a mapping relationship which maps a physical address within a target block to a logical address of a sector of user data stored at the physical address. The control unit performs reverse conversion on the mapping relationship to get reversed mapping information for the logical address and, accordingly, selects a target logical-to-physical mapping sub-table. A second buffer is provided to buffer the target logical-to-physical mapping sub-table when the target logical-to-physical mapping sub-table is read from the host memory buffer HMB. The control unit updates the target logical-to-physical mapping sub-table on the second buffer based on the reversed mapping information about the logical address.

    Firmware Updating Method
    192.
    发明申请

    公开(公告)号:US20200012487A1

    公开(公告)日:2020-01-09

    申请号:US16360034

    申请日:2019-03-21

    Inventor: Chien-Ting LIN

    Abstract: A firmware updating method is provided. The firmware updating method is adapted to a data storage device, and it can generate a new parameter table according to a conversion formula segment in an update image file required for updating the data storage device. Therefore, even if in a condition where there is a parameter change between a code segment of an old version firmware and a code segment of a new version firmware, the updated or upgraded data storage device can still operate normally.

    Method employed in LDPC decoder and the decoder

    公开(公告)号:US10523236B2

    公开(公告)日:2019-12-31

    申请号:US15820391

    申请日:2017-11-21

    Inventor: Shiuan-Hao Kuo

    Abstract: A method employed in a low-density parity-check code decoder includes: receiving a specific data portion of a first codeword; calculating a flipping function value of the specific data portion of the first codeword according to the specific data portion by using checking equations of a parity check matrix to calculate checking values of the specific data portion; and determining whether to flip the specific data portion of the first codeword by comparing the flipping function value with a flipping threshold which has been calculated based on a plurality of flipping function values of a plurality of previous data portions earlier than the specific data portion.

    Flash memory controller
    194.
    发明授权

    公开(公告)号:US10521142B2

    公开(公告)日:2019-12-31

    申请号:US16260142

    申请日:2019-01-29

    Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.

    METHOD AND APPARATUS FOR PERFORMING OPERATIONS TO NAMESPACES OF A FLASH MEMORY DEVICE

    公开(公告)号:US20190391928A1

    公开(公告)日:2019-12-26

    申请号:US16164252

    申请日:2018-10-18

    Inventor: Sheng-Liu LIN

    Abstract: The invention introduces a method for performing operations to namespaces of a flash memory device, at least including the steps: receiving a namespace setting-update command from a host, requesting to update a namespace size of a namespace; determining whether the updated namespace size of the namespace can be supported; and when the updated namespace size of the namespace can be supported, updating a logical-physical mapping table of the namespace to enable the namespace to store user data of the updated namespace size.

    Data storage device and method for operating data storage device with efficient trimming operations

    公开(公告)号:US10481837B2

    公开(公告)日:2019-11-19

    申请号:US15813573

    申请日:2017-11-15

    Inventor: Cheng-Yi Lin

    Abstract: A data storage device with improved space-trimming capability. A microcontroller operating in accordance with a host allocates a non-volatile memory to store data. The microcontroller manages the mapping information between the logical addresses used by the host and the space of the non-volatile memory. The microcontroller further takes responsibility for the transformation of a trimming command that is issued by the host to invoke a plurality of trimming requests. After the transformation, a target-host block repeatedly indicated by the plurality of trimming requests is transformed to be trimmed at one time. The mapping information of the target-host block, therefore, is not read frequently from the non-volatile memory for real-time amendment.

    Memory control device and method
    197.
    发明授权

    公开(公告)号:US10474364B2

    公开(公告)日:2019-11-12

    申请号:US16016134

    申请日:2018-06-22

    Inventor: Yao-Pang Chiang

    Abstract: A memory control device and method are provided in the invention. The controller of the memory control device includes a static random access memory (SRAM) which has a first buffer. The controller receives a command from a host device, determines the operation type indicated by the command, and obtains data parameters corresponding to data stored in the SRAM. The DRAM is coupled to the controller and has a second buffer. The controller determines whether the first buffer is enough to store data corresponding to the command according to the data parameters. When the first buffer is not enough to store data corresponding to the command, the controller backs up data corresponding to another operation type to the second buffer, and the controller temporarily stores the data corresponding to the command, and updates the data parameters.

    METHOD FOR CONTROLLING STORAGE DEVICE WITH AID OF ERROR CORRECTION AND ASSOCIATED APPARATUS

    公开(公告)号:US20190341937A1

    公开(公告)日:2019-11-07

    申请号:US16516268

    申请日:2019-07-19

    Inventor: Tsung-Chieh Yang

    Abstract: A method for decoding an error correction code and an associated decoding circuit are provided, where the method includes the steps of: calculating a set of error syndromes of the error correction code, where the error correction code is a t-error correcting code and has capability of correcting t errors, and a number s of the set of error syndromes is smaller than t; sequentially determining a set of coefficients within a plurality of coefficients of an error locator polynomial of the error correction code according to at least one portion of error syndromes within the set of error syndromes for building a roughly-estimated error locator polynomial; performing a Chien search to determine a plurality of roots of the roughly-estimated error locator polynomial; and performing at least one check operation to selectively utilize a correction result of the error correction code as a decoding result of the error correction code.

    DATA STORAGE SYSTEM AND CALIBRATION METHOD FOR OPERATIONAL INFORMATION USED IN CONTROLLING NON-VOLATILE MEMORY

    公开(公告)号:US20190332547A1

    公开(公告)日:2019-10-31

    申请号:US16170265

    申请日:2018-10-25

    Inventor: Chun-Yi LO

    Abstract: A technology for calibrating device-end operational information of a data storage system is shown. A controller operates a non-volatile memory with reference to operational information. A second type of logical address requested by the host that is different from the first type of logical address used in operating a file system of a host is introduced. As indicated by the second type of logical address, the controller receives calibration information from the host and calibrates the operational information based on the calibration information.

    Data storage device with production state awareness and non-volatile memory operating method with production state awareness

    公开(公告)号:US10459837B2

    公开(公告)日:2019-10-29

    申请号:US15853429

    申请日:2017-12-22

    Inventor: Shen-Ting Chiu

    Abstract: A data-downloading technique for a data storage device before soldering the data storage device into a product. The data storage device uses a flash memory to provide first-type blocks (using single level cells) and second-type blocks (using multi-level cells). Before soldering the data storage device onto a printed circuit board, a controller of the data storage device allocates the first-type blocks to store data from a host. When the allocated number of first-type blocks reaches an upper limit, the controller changes to allocate the second-type blocks to store data from the host. When detecting that the controller has changed to allocate the flash memory to provide the second-type blocks to receive data from the host, the controller returns a fail message to the host to indicate unreliable write operations prior to soldering.

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