Abstract:
A method of fabricating a semiconductor device is provided which includes providing a substrate. A material layer is formed over the substrate. A polymer layer is formed over the material layer. A nano-sized feature is self-assembled using a portion of the polymer layer. The substrate is patterned using the nano-sized feature.
Abstract:
A method of performing immersion lithography on a semiconductor substrate includes providing a layer of resist onto a surface of the semiconductor substrate and exposing the resist layer using an immersion lithography exposure system. The immersion lithography exposure system utilizes a fluid during exposure and may be capable of removing some, but not all, of the fluid after exposure. After exposure, a treatment process is used to neutralize the effect of undesired elements that diffused into the resist layer during the immersion exposure. After treatment, a post-exposure bake and a development step are used.
Abstract:
Various lithography methods are disclosed. An exemplary lithography method includes forming a first patterned silicon-containing organic polymer layer over a substrate by removing a first patterned resist layer, wherein the first patterned silicon-containing organic polymer layer includes a first opening having a first dimension and a second opening having the first dimension, the first opening and the second opening exposing the substrate; forming a second patterned silicon-containing organic polymer layer over the substrate by removing a second patterned resist layer, wherein a portion of the patterned second silicon-containing organic polymer layer combines with a portion of the first patterned silicon-containing organic polymer layer to reduce the first dimension of the second opening to a second dimension; and etching the substrate exposed by the first opening having the first dimension and the second opening having the second dimension.
Abstract:
Immersion lithography system and method using a sealed wafer bottom are described. One embodiment is an immersion lithography apparatus comprising a lens assembly comprising an imaging lens and a wafer stage for retaining a wafer beneath the lens assembly, the wafer stage comprising a seal ring disposed on a seal ring frame along a top edge of the wafer retained on the wafer stage, the seal ring for sealing a gap between an edge of the wafer and the wafer stage. The embodiment further includes a fluid tank for retaining immersion fluid, the fluid tank situated with respect to the wafer stage for enabling full immersion of the wafer retained on the wafer stage in the immersion fluid and a cover disposed over at least a portion of the fluid tank for providing a temperature-controlled, fluid-rich environment within the fluid tank; and
Abstract:
Immersion lithography system and method using direction-controlling fluid inlets are described. According to one embodiment of the present disclosure, an immersion lithography apparatus includes a lens assembly having an imaging lens disposed therein and a wafer stage configured to retain a wafer beneath the lens assembly. The apparatus also includes a plurality of direction-controlling fluid inlets disposed adjacent to the lens assembly, each direction-controlling fluid inlet in the plurality of direction-controlling fluid inlets being configured to direct a flow of fluid beneath the lens assembly and being independently controllable with respect to the other fluid inlets in the plurality of direction-controlling fluid inlets.
Abstract:
A method of semiconductor fabrication including an etching process is provided. The method includes providing a substrate and forming a target layer on the substrate. An etchant layer is formed on the target layer. The etchant layer reacts with the target layer and etches a portion of the target layer. In an embodiment, an atomic layer of the target layer is etched. The etchant layer is then removed from the substrate. The process may be iterated any number of times to remove a desired amount of the target layer. In an embodiment, the method provides for decreased lateral etching. The etchant layer may provide for improved control in forming patterns in thin target layers such as, capping layers or high-k dielectric layers of a gate structure.
Abstract:
The present invention includes a lithography method comprising forming a first patterned resist layer including at least one opening therein over a substrate. A protective layer is formed on the first patterned resist layer and the substrate whereby a reaction occurs at the interface between the first patterned resist layer and the protective layer to form a reaction layer over the first patterned resist layer. The non-reacted protective layer is then removed. Thereafter, a second patterned resist layer is formed over the substrate, wherein at least one portion of the second patterned resist layer is disposed within the at least one opening of the first patterned resist layer. The substrate is thereafter etched using the first and second patterned resist layers as a mask.
Abstract:
An anti-reflective coating comprises a plurality of main backbone chains, and at least one long free polymer chain coupled to at least one of the plurality of main backbone chains.
Abstract:
A method of fabricating a semiconductor device is provided which includes providing a substrate. A material layer is formed over the substrate. A polymer layer is formed over the material layer. A nano-sized feature is self-assembled using a portion of the polymer layer. The substrate is patterned using the nano-sized feature.
Abstract:
An immersion lithography resist material comprising a matrix polymer having a first polarity and an additive having a second polarity that is substantially greater than the first polarity. The additive may have a molecular weight that is less than about 1000 Dalton. The immersion lithography resist material may have a contact angle that is substantially greater than the contact angle of the matrix polymer.