公开(公告)号：US20250054531A1

公开(公告)日：2025-02-13

申请号：US18930833

申请日：2024-10-29

Applicant: Micron Technology, Inc.

Inventor： Tong Liu ,  Daniele Vimercati

IPC: G11C11/22

Abstract: Systems and methods are related to a memory device including a plate line. The memory device also includes a pair of ferroelectric layers implementing a pair of memory cells and coupled to opposite sides of the plate line. The memory device further includes a pair of digit lines each coupled to a respective ferroelectric layer of the pair of ferroelectric layers. The memory device also includes a sense amplifier coupled to the pair of digit lines and configured to sense and amplify voltages received at the digit lines from the respective memory cells. The sense amplifier includes a threshold voltage compensated latch that includes multiple p-channel transistors and is configured to compensate for process, voltage, or temperature variation mismatches between the threshold voltages of the multiple p-channel transistors.

公开(公告)号：US20250053630A1

公开(公告)日：2025-02-13

申请号：US18933096

申请日：2024-10-31

Applicant: Micron Technology, Inc.

Inventor： Bhumika Chhabra ,  Carla L. Christensen ,  Radhika Viswanathan ,  Zahra Hosseinimakarem

IPC: G06F21/32 ,  G06F21/60 ,  G06V40/12 ,  G06V40/16 ,  G06V40/18 ,  G09G3/3208

Abstract: Methods, apparatuses, and non-transitory machine-readable media for displaying information and/or images on a display of a computing device based on received data. Apparatuses can include a display screen, a memory resource, a recognition sensor, and a controller. An example controller can receive data and activate information and/or images on a display screen based in part on the received data. In another example, a method can include storing recognition data in a memory resource, receiving primary recognition data, comparing the primary recognition data to the stored recognition data, and activating the display screen for a viewing angle responsive to authentication of the primary recognition data through the comparison of the primary recognition data and the stored recognition data.

公开(公告)号：US20250053512A1

公开(公告)日：2025-02-13

申请号：US18777466

申请日：2024-07-18

Applicant: Micron Technology, Inc.

Inventor： Robert M. Walker

IPC: G06F12/06

Abstract: Mapping addresses to banks can include receiving a plurality of row bits, a plurality of column bits, and a plurality of bank bits and generating a rank bit from a bank bit from the plurality of bank bits. Updated bank bits can be generated by removing the bank bit from the plurality of bank bits. The plurality of row bits, the plurality of column bits, the rank bit, and the updated bank bits can be provided to the controller to access a plurality of banks of the memory device.

公开(公告)号：US20250053506A1

公开(公告)日：2025-02-13

申请号：US18778627

申请日：2024-07-19

Applicant: Micron Technology, Inc.

Inventor： Emanuele CONFALONIERI ,  Marco SFORZIN

IPC: G06F12/02

Abstract: Provided is a device that includes an interface operatively coupled to a locked redundant array of independent disks including M (M>1) memory dice, the M memory dice stores stripes of data, and each stripe spanning over the M memory dice; and control circuitry that performs data compression on data to generate compressed data; stores the compressed data in the stripes; generates parity data of each stripe; determines, for each stripe, memory dice required to store the compressed data; determines, for each stripe, whether the memory dice required to store the compressed data in each stripe is N memory dice or less; where N is an integer less than M; and determines, for each stripe, which stripes will store the parity data of a respective stripe based on the determination of whether the memory dice required to store the compressed data in the respective stripe is N memory dice or less.

公开(公告)号：US20250053344A1

公开(公告)日：2025-02-13

申请号：US18929602

申请日：2024-10-28

Applicant: Micron Technology, Inc.

Inventor： Eldhose Peter

IPC: G06F3/06

Abstract: A system includes a memory device configured with a zoned namespace having a plurality of zones, and a processing device, operatively coupled with the memory device, to perform operations comprising storing, in a first queue of the memory device, a first identifier of a first memory access operation to be performed at a first zone of the memory device, identifying one of a plurality of plane sets of the memory device that is associated with the first zone of the memory device, identifying a second queue of the memory device, wherein the second queue corresponds to the identified plane set, responsive to determining that a number of identifiers of memory access operations stored in the second queue satisfies a threshold criterion, retrieving, from the second queue, a second identifier of a second memory access operation to be performed at a second zone of the memory device, storing the second identifier of the second memory access operation in a third queue of the memory device, and performing the second memory access operation at the second zone associated with a second plane set of the memory device.

公开(公告)号：US20250053342A1

公开(公告)日：2025-02-13

申请号：US18927374

申请日：2024-10-25

Applicant: Micron Technology, Inc.

Inventor： Shanyuan Gao ,  Sen Ma ,  Moon Mark Hur ,  Jaime Cummins

IPC: G06F3/06

Abstract: Methods, systems, and apparatuses related to computational storage are described. For example, storage accessible to an accelerator may be shared between and, accessible to either of, a host and the accelerator. A computational storage system may include storage providing a portion of a shared file system accessible by a host and by accelerator logic of the computational storage system. Host interface logic may be configured to receive a storage command from the host to store data on the storage at a time the data is created. The host interface logic may be further configured to receive a storage command from the host for the accelerator logic to perform a computational task using the stored data on the storage. The accelerator logic can perform the computational task using the stored data on the storage.

公开(公告)号：US20250053341A1

公开(公告)日：2025-02-13

申请号：US18789249

申请日：2024-07-30

Applicant: Micron Technology, Inc.

Inventor： Gyan Prakash ,  Jose Rey C. De Luna

IPC: G06F3/06

Abstract: A method includes receiving, by a memory device interface, a first operation command targeted for receipt by a memory device coupled to the memory device interface causing, responsive to receiving the first operation command, a chip enable signal to be asserted in a first state to filter commands received by the memory device interface that are targeted for subsequent receipt by the memory device, receiving, by the memory device interface, a second operation command targeted for receipt by a memory device coupled to the memory device interface, and causing, responsive to receiving the second operation command, the chip enable signal to be asserted in a second state to allow commands received by the memory device interface that are targeted for subsequent receipt by the memory device to be received by the memory device.

公开(公告)号：US20250053329A1

公开(公告)日：2025-02-13

申请号：US18786812

申请日：2024-07-29

Applicant: Micron Technology, Inc.

Inventor： Sampath Ratnam ,  Daniel J. Hubbard ,  Kevin R. Brandt ,  David Ebsen ,  Brent Carl Byron

IPC: G06F3/06

Abstract: Aspects of the present disclosure configure a memory sub-system controller to receive information from a host about invalidated memory addresses. The controller receives, from a host, data identifying a set of storage locations associated with invalidated data stored in a set of memory components and, in response to receiving the data, performs staging activity for the invalidated data stored in the set of storage locations. The controller receives, from the host, a trim command for one or more storage locations in the set of storage locations and performs trim operations for the one or more storage locations for which the staging activity has already been performed.

公开(公告)号：US20250053327A1

公开(公告)日：2025-02-13

申请号：US18806210

申请日：2024-08-15

Applicant: Micron Technology, Inc.

Inventor： Alan J. Wilson ,  Donald M. Morgan

IPC: G06F3/06 ,  G06F12/10

Abstract: Methods, systems, and devices for repair operation techniques are described. A memory device may detect a failure of a read operation associated with a physical row address of a memory die. The memory device may store information associated with the physical row address before performing a media management operation and after detecting the failure. Additionally or alternatively, the memory device may initiate a counter based on detecting the failure and may increment a value of the counter for each media management operation performed after detecting the failure. The memory device may send a command or other information to perform a repair operation for the physical row address. The memory device may determine the physical row address for the repair operation (e.g., despite media management operations) based on the stored information or the value of the counter, and may perform the repair operation on the physical row address.

公开(公告)号：US12225721B2

公开(公告)日：2025-02-11

申请号：US17841925

申请日：2022-06-16

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Nancy M. Lomeli

IPC: H10B41/27 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. A stack comprising vertically-alternating first tiers and second tiers is formed above the conductor tier. The stack comprises laterally-spaced memory-block regions. Channel-material strings extend through the first tiers and the second tiers. Material of the first tiers is of different composition from material of the second tiers. Spaced insulator-material bodies are formed in and longitudinally-along opposing sides of individual of the memory-block regions in a lowest of the first tiers. After forming the spaced insulator-material bodies, conductive material is formed in the lowest first tier that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. Other embodiments, including structure independent of method, are disclosed.