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公开(公告)号：US11641191B2
公开(公告)日：2023-05-02
申请号：US17830864
申请日：2022-06-02
Applicant: STMicroelectronics S.r.l. , STMicroelectronics (Alps) SAS
Inventor： Antonino Conte , Marco Ruta , Michelangelo Pisasale , Thomas Jouanneau
Abstract: In an embodiment a ring oscillator circuit includes a chain of cascade-coupled inverter stages coupled between an oscillator supply voltage node and a reference voltage node, the oscillator supply voltage node configured to provide an oscillator supply voltage, a current generator circuit coupled between the oscillator supply voltage node and a system supply voltage node configured to provide a system supply voltage, the current generator circuit being configured to inject a current into the oscillator supply voltage node and a biasing circuit including a first bias control transistor and a second bias control transistor coupled in series between the reference voltage node and the oscillator supply voltage node, wherein the first bias control transistor is configured to selectively couple the reference voltage node and the oscillator supply voltage node in response to the oscillator control signal being indicative that the ring oscillator circuit is in an inactive operation state.
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202.发明授权公开(公告)号：US11610025B2
公开(公告)日：2023-03-21
申请号：US17161194
申请日：2021-01-28
Inventor： Gilles Pelissier , Nicolas Anquet , Delphine Le-Goascoz
Abstract: An integrated circuit includes a secure hardware environment having a first input that receives a key number. A key generation device generates a secret key from the key number and a unique key. A signature generation device generates a signature associated with the key number. A second input of the secure hardware environment receives encrypted binary data. A decryption device operates to decrypt the received encrypted binary data using the secret key. A third input the secure hardware environment receives an authentication signature. An authentication device authorizes use of the secret key to decrypt only if the signature generated by the signature generation device is identical to the authentication signature.
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公开(公告)号：US20230056937A1
公开(公告)日：2023-02-23
申请号：US17881749
申请日：2022-08-05
Inventor： Danika Perrin , Sandrine Nicolas
IPC: H04B1/16
Abstract: In an embodiment an envelope detection device includes an input terminal configured to receive an amplitude-modulated radio frequency signal, a first resistive element and a first MOS transistor connected in parallel between the input terminal and a first node configured to receive a reference potential, a first capacitive element connected between a gate of the first MOS transistor and the first node, an envelope detection circuit connected to the input terminal and configured to supply a voltage representative of an envelope of the amplitude-modulated signal and a circuit for controlling the first MOS transistor configured to supply a first current to the gate of the first MOS transistor only when the voltage is smaller than a first threshold and draw a second current from the gate of the first MOS transistor only when the voltage is higher than a second threshold, the second threshold being higher than the first threshold.
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公开(公告)号：US20230018356A1
公开(公告)日：2023-01-19
申请号：US17812062
申请日：2022-07-12
Inventor： Hugo Gicquel , Sandrine Nicolas , Cedric Rechatin , Reiner Welk
IPC: H03F3/193
Abstract: In an embodiment an amplifier includes a first MOS transistor having a drain connected to an output of the amplifier and a source coupled to a first node configured to receive a first power supply potential, a first capacitive element connected between an input of the amplifier and a gate of the first MOS transistor, a first current source connecting the drain of the first MOS transistor to a second node configured to receive a second power supply potential and a resistive element and a second capacitive element connected in parallel between the gate and the drain of the first MOS transistor, the resistive element including a switched capacitor.
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公开(公告)号：US11533019B2
公开(公告)日：2022-12-20
申请号：US17180752
申请日：2021-02-20
Applicant: STMicroelectronics (Grenoble 2) SAS , STMicroelectronics S.r.l. , STMicroelectronics (Rousset) SAS , STMicroelectronics (Alps) SAS
Abstract: The present disclosure relates to an electronic device comprising a first capacitor and a quartz crystal coupled in series between a first node and a second node; an inverter coupled between the first and second nodes; a first variable capacitor coupled between the first node and a third node; and a second variable capacitor coupled between the second node and the third node.
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Patent Agency Ranking
206.发明授权公开(公告)号：US11522360B2
公开(公告)日：2022-12-06
申请号：US17202566
申请日：2021-03-16
Applicant: STMicroelectronics (Alps) SAS
Inventor： Frederic Lebon , Laurent Chevalier
Abstract: An electronic circuit includes a switch coupled between an input terminal intended to receive a first voltage and an output terminal coupled to a decoupling capacitor and intended to also be coupled to a load. A comparison stage is configured to compare the first voltage and a second voltage that is present at the output terminal. A first adjustment stage is configured to limit a positive inrush current flowing between the input terminal and the output terminal and a second adjustment stage is configured to limit a negative inrush current flowing between the output terminal and the input terminal. A control circuit is configured to activate either the first adjustment stage or the second adjustment stage as a function of a result of the comparison.
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公开(公告)号：US11469671B2
公开(公告)日：2022-10-11
申请号：US17324782
申请日：2021-05-19
Applicant: STMicroelectronics (Alps) SAS
Inventor： Thomas Jouanneau
Abstract: The integrated circuit includes a first node intended to be biased at a first voltage, a second node intended to be biased at a second voltage and having a non-negligible capacitive coupling with the first node. A power supply management device comprises a voltage booster configured to boost a power supply voltage and comprising boost stages configured to generate intermediate voltages on intermediate nodes. A compatibility detection circuit is configured to detect compatibility between the second voltage and one of the intermediate voltages, and, if the second voltage is compatible with an intermediate voltage, to couple the at least one second node to the compatible intermediate node.
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公开(公告)号：US20220318392A1
公开(公告)日：2022-10-06
申请号：US17657027
申请日：2022-03-29
Inventor： Franck Albesa , Nicolas Anquet
IPC: G06F21/57 , G06F21/60 , G06F9/4401
Abstract: The present disclosure relates to a method for booting a processing device, the method including: generating, by a monotonic counter and during a first boot phase, a first count value; transmitting, by the monotonic counter, the first count value to an access control circuit of a memory; reading, on the basis of the first count value, first data stored in the memory; and generating, by the monotonic counter and during a second boot phase, a second count value greater than the first count value. The access control circuit of the memory is configured so that the reading of the first data is not authorized on the basis of the second count value.
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公开(公告)号：US20220198005A1
公开(公告)日：2022-06-23
申请号：US17644711
申请日：2021-12-16
Inventor： Diana Moisuc , Christophe Eichwald
Abstract: Method for detecting the linear extraction of information in a processor using an instruction pointer. The method includes monitoring the values of the instruction pointer, determining a number of consecutive increments incrementing the values of the instruction pointer by a constant amount, and generating a detection signal if the number is greater than or equal to a detection threshold.
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公开(公告)号：US20220180004A1
公开(公告)日：2022-06-09
申请号：US17544038
申请日：2021-12-07
Applicant: STMICROELECTRONICS SA , STMicroelectronics (Alps) SAS
Inventor： Julien Goulier , Pascal Bernon
Abstract: The present description concerns an integrated circuit including, between first and second terminals having a first voltage applied therebetween, a load configured to execute instructions, a circuit for delivering a digital signal having at least two bits from a binary signal and a current output digital-to-analog converter controlled by the digital signal and coupled between the first and second terminals in parallel with the load.
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