公开(公告)号：US10892209B2

公开(公告)日：2021-01-12

申请号：US16363468

申请日：2019-03-25

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Nazila Dadvand ,  Sreenivasan Koduri

IPC: H01L23/495 ,  H01L21/48

Abstract: A semiconductor device includes a metal substrate including a through-hole aperture having a multi-size cavity including a larger area first cavity portion above a smaller area second cavity portion that defines a first ring around the second cavity portion, where the first cavity portion is sized with area dimensions to receive a semiconductor die having a top side with circuitry coupled to bond pads thereon and a back side with a metal (BSM) layer thereon. The semiconductor die is mounted top side up with the BSM layer on the first ring. A metal die attach layer directly contacts the BSM layer, sidewalls of the bottom cavity portion, and a bottom side of the metal substrate.

公开(公告)号：US20210005537A1

公开(公告)日：2021-01-07

申请号：US17027657

申请日：2020-09-21

Applicant: Texas Instruments Incorporated

Inventor： Kurt Peter Wachtler ,  Seunghyun Chae ,  Benjamin Stassen Cook

IPC: H01L23/495 ,  H01L23/00

Abstract: An integrated circuit die may be fabricating to have a plurality of contacts. A metal post may be formed on each of the plurality of contacts. A plurality of bumps may be formed on a plurality of contact regions of a leadframe or on the posts, in which the plurality of bumps are formed with a material that includes metal nanoparticles. The IC die may be attached to the leadframe by aligning the metal posts to the leadframe and sintering the metal nanoparticles in the plurality of bumps to form a sintered metal bond between each metal post and corresponding contact region of the leadframe.

公开(公告)号：US10861715B2

公开(公告)日：2020-12-08

申请号：US16236099

申请日：2018-12-28

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Daniel Lee Revier

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/66 ,  H01L23/495 ,  H01L23/00

Abstract: In described examples, a method for encapsulating a semiconductor device includes the steps of immersing a layer of the semiconductor device in a liquid encapsulation material, irradiating portions of the liquid encapsulation material to polymerize the liquid encapsulation material, and moving the semiconductor device further from a surface of the liquid encapsulation material proximate to the layer. Immersing the semiconductor device is performed to cover a layer of the device in the liquid encapsulation material. Targeted locations of the liquid encapsulation material covering the layer are irradiated to form solid encapsulation material. The semiconductor device is moved from a surface of the liquid encapsulation material so that a new layer of the semiconductor device and/or of the solid encapsulation material can be covered by the liquid encapsulation material. The irradiating and moving steps are then repeated until a three dimensional structure on the semiconductor device is formed using the solid encapsulation material.

公开(公告)号：US10832993B1

公开(公告)日：2020-11-10

申请号：US16408108

申请日：2019-05-09

Applicant: Texas Instruments Incorporated

Inventor： Nazila Dadvand ,  Sreenivasan Koduri ,  Benjamin Stassen Cook

IPC: H01L23/495 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31

Abstract: A leadless multichip semiconductor device includes a metal substrate having a through-hole aperture with an outer ring for holding a bottom semiconductor die with an inner row and an outer row of metal pads. The bottom semiconductor die has a back side metal (BSM) layer on its bottom side and a top side with bond pads mounted top side up on the ring. A metal die attach layer is directly between the BSM layer and walls of the metal substrate providing a die attachment that fills a bottom portion of the aperture. Bond wires are between the inner metal pads and the bond pads. A top semiconductor die has top bond pads mounted top side up on a dielectric adhesive on the bottom semiconductor die. Pins connect the top bond pads to the outer metal pads. A mold compound provides isolation between adjacent ones of the metal pads.

公开(公告)号：US10811334B2

公开(公告)日：2020-10-20

申请号：US15361394

申请日：2016-11-26

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Archana Venugopal ,  Luigi Colombo ,  Robert Reid Doering

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/495 ,  H01L23/34 ,  H01L23/367 ,  H01L23/373 ,  H01L21/48 ,  H01L21/768 ,  H01L23/522 ,  H01L23/00 ,  H01L23/532

Abstract: An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region has a plurality of interconnect levels. The integrated circuit includes a thermal routing structure in the interconnect region. The thermal routing structure extends over a portion, but not all, of the integrated circuit in the interconnect region. The thermal routing structure includes a cohered nanoparticle film in which adjacent nanoparticles cohere to each other. The thermal routing structure has a thermal conductivity higher than dielectric material touching the thermal routing structure. The cohered nanoparticle film is formed by a method which includes an additive process.

公开(公告)号：US10692964B2

公开(公告)日：2020-06-23

申请号：US16023377

申请日：2018-06-29

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Roberto Giampiero Massolini ,  Daniel Carothers

IPC: H01L21/00 ,  H01L49/02 ,  H01L23/495 ,  H01L27/06 ,  H01L21/3065 ,  H01L21/768 ,  H01L23/498 ,  H01L23/00

Abstract: An integrated circuit (IC) includes a circuit substrate having a front side surface and an opposite back side surface. Active circuitry is located on the front side surface. An inductive structure is located within a deep trench formed in the circuit substrate below the backside surface. The inductive structure is coupled to the active circuitry.

公开(公告)号：US20200162127A1

公开(公告)日：2020-05-21

申请号：US16773557

申请日：2020-01-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Benjamin Stassen Cook ,  Swaminathan Sankaran

IPC: H04B5/00 ,  H01P5/107

Abstract: A system is provided in which a first waveguide has a first resonator coupled to an end of the first waveguide. A second waveguide has a second resonator coupled to the second waveguide. The first resonator is spaced apart from the second resonator by a gap distance. Transmission of a signal propagated by the first waveguide across the gap to the second waveguide is enhanced by a confined near field mode magnetic field produced by the first resonator in response to the propagating wave that is coupled to the second resonator.

公开(公告)号：US10589986B2

公开(公告)日：2020-03-17

申请号：US15696245

申请日：2017-09-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Adam Joseph Fruehling ,  Juan Alejandro Herbsommer ,  Simon Joshua Jacobs ,  Benjamin Stassen Cook ,  James F. Hallas ,  Randy Long

IPC: B81B7/00 ,  H03L7/26 ,  G01L7/08 ,  G04F5/14 ,  G01M3/32 ,  G01L9/00

Abstract: An electronic device includes a package substrate, a circuit assembly, and a housing. The circuit assembly is mounted on the package substrate. The circuit assembly includes a first sealed cavity formed in a device substrate. The housing is mounted on the package substrate to form a second sealed cavity about the circuit assembly.

公开(公告)号：US10553573B2

公开(公告)日：2020-02-04

申请号：US15693985

申请日：2017-09-01

Applicant: Texas Instruments Incorporated

Inventor： Daniel Lee Revier ,  Steven Alfred Kummerl ,  Benjamin Stassen Cook

IPC: H01L23/31 ,  H01L23/367 ,  H01L23/495 ,  H01F7/02 ,  H01F7/20 ,  H01L25/00 ,  H01L21/687

Abstract: Integrated circuits may be assembled by placing a batch of integrated circuit (IC) die on a leadframe. Each of the IC die includes a magnetically responsive structure that may be an inherent part of the IC die or may be explicitly added. The IC die are then agitated to cause the IC die to move around on the leadframe. The IC die are captured in specific locations on the leadframe by an array of magnetic domains that produce a magnetic response from the plurality of IC die. The magnetic domains may be formed on the lead frame, or may be provided by a magnetic chuck positioned adjacent the leadframe.

公开(公告)号：US10529796B2

公开(公告)日：2020-01-07

申请号：US16178352

申请日：2018-11-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Benjamin Stassen Cook ,  Barry Jon Male ,  Robert Alan Neidorff

IPC: H01L49/02 ,  H01L23/66 ,  H01L23/495

Abstract: A galvanic isolation device includes a first integrated circuit (IC) die that has communication circuitry formed in a circuit layer below the top surface. A first conductive plate is formed on the IC die proximate the top surface, and is coupled to the communication circuitry. A dielectric isolation layer is formed over a portion of the top surface of the IC after the IC is fabricated such that the dielectric isolation layer completely covers the conductive plate. A second conductive plate is juxtaposed with the first conductive plate but separated by the dielectric isolation layer such that the first conductive plate and the second conductive plate form a capacitor. The second conductive plate is configured to be coupled to a second communication circuit.