公开(公告)号：US20200303285A1

公开(公告)日：2020-09-24

申请号：US16359628

申请日：2019-03-20

Applicant: Texas Instruments Incorporated

Inventor： Nazila Dadvand ,  Sreenivasan Koduri ,  Benjamin Stassen Cook

IPC: H01L23/495 ,  H01L23/13 ,  H01L23/00 ,  H01L23/31 ,  H01L23/14 ,  H01L25/18 ,  H01L21/56 ,  H01L21/48 ,  H01L25/065 ,  C25D7/12 ,  C25D3/38

Abstract: A packaged semiconductor device includes a metal substrate having a first and second through-hole aperture having an outer ring, and metal pads around the apertures on dielectric pads. A first and second semiconductor die have a back side metal (BSM) layer on its bottom side are mounted top side up on a top portion of the apertures. A metal die attach layer is directly between the BSM layer and walls of the metal substrate bounding the apertures to provide a die attachment for the first and the second semiconductor die that fills a bottom portion of the apertures. Leads contact the metal pads, wherein the leads include a distal portion that extends beyond the metal substrate. Bondwires are between the metal pads and bond pads on the first and second semiconductor die, and a mold compound provides encapsulation for the packaged semiconductor device.

公开(公告)号：US12040249B2

公开(公告)日：2024-07-16

申请号：US16731709

申请日：2019-12-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sreenivasan Koduri

IPC: H01L23/367 ,  H01L21/48 ,  H01L21/56 ,  H01L23/13 ,  H01L23/14 ,  H01L23/31 ,  H01L23/482 ,  H01L23/485 ,  H01L25/065 ,  H01L25/16

CPC classification number: H01L23/3675 ,  H01L21/4875 ,  H01L21/565 ,  H01L23/13 ,  H01L23/142 ,  H01L23/3121 ,  H01L23/4827 ,  H01L23/485 ,  H01L25/0655 ,  H01L25/16

Abstract: A package comprises a platform and at least one pedestal positioned along at least a portion of a perimeter of the platform. The platform and the at least one pedestal form a cavity. The package further comprises a die positioned in the cavity and on the platform, with the die having an active circuit facing away from the platform. The package also comprises a conductive layer coupled to the die and to a conductive terminal. The conductive terminal is positioned above the at least one pedestal, and the die and the conductive terminal are positioned in different horizontal planes.

公开(公告)号：US20200312747A1

公开(公告)日：2020-10-01

申请号：US16363468

申请日：2019-03-25

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Nazila Dadvand ,  Sreenivasan Koduri

IPC: H01L23/495 ,  H01L23/00 ,  H01L21/48

Abstract: A semiconductor device includes a metal substrate including a through-hole aperture having a multi-size cavity including a larger area first cavity portion above a smaller area second cavity portion that defines a first ring around the second cavity portion, where the first cavity portion is sized with area dimensions to receive a semiconductor die having a top side with circuitry coupled to bond pads thereon and a back side with a metal (BSM) layer thereon. The semiconductor die is mounted top side up with the BSM layer on the first ring. A metal die attach layer directly contacts the BSM layer, sidewalls of the bottom cavity portion, and a bottom side of the metal substrate.

公开(公告)号：US20240096771A1

公开(公告)日：2024-03-21

申请号：US17946109

申请日：2022-09-16

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Lopez ,  Salvatore Pavone ,  Sreenivasan Koduri

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/16

CPC classification number: H01L23/49805 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/16 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L25/165 ,  H01L23/3738 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L2224/95001

Abstract: An electronic device includes a multilevel metallization structure, a semiconductor die, and a package structure. The multilevel metallization structure has multiple levels of conductive metal traces and vias and polyimide insulator material, including a first level along a first side and a final level along a second side. The first level includes conductive metal leads with exposed surfaces along the first side, and the final level includes conductive metal pads with exposed surfaces along the second side. The semiconductor die is flip chip attached to the first side of the multilevel metallization structure with conductive features connected to respective conductive metal pads of the final level of the multilevel metallization structure, and the package structure encloses the semiconductor die and portions of the first side of the multilevel metallization structure.

公开(公告)号：US11908776B2

公开(公告)日：2024-02-20

申请号：US17142598

申请日：2021-01-06

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Nazila Dadvand ,  Sreenivasan Koduri

IPC: H01L23/495 ,  H01L21/48

CPC classification number: H01L23/49513 ,  H01L21/4871 ,  H01L23/49503 ,  H01L23/49548 ,  H01L23/49568 ,  H01L23/49582 ,  H01L2224/32245

Abstract: A semiconductor device includes a metal substrate including a through-hole aperture having a multi-size cavity including a larger area first cavity portion above a smaller area second cavity portion that defines a first ring around the second cavity portion, where the first cavity portion is sized with area dimensions to receive a semiconductor die having a top side with circuitry coupled to bond pads thereon and a back side with a metal (BSM) layer thereon. The semiconductor die is mounted top side up with the BSM layer on the first ring. A metal die attach layer directly contacts the BSM layer, sidewalls of the bottom cavity portion, and a bottom side of the metal substrate.

公开(公告)号：US20210125902A1

公开(公告)日：2021-04-29

申请号：US17142598

申请日：2021-01-06

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Nazila Dadvand ,  Sreenivasan Koduri

IPC: H01L23/495 ,  H01L21/48

Abstract: A semiconductor device includes a metal substrate including a through-hole aperture having a multi-size cavity including a larger area first cavity portion above a smaller area second cavity portion that defines a first ring around the second cavity portion, where the first cavity portion is sized with area dimensions to receive a semiconductor die having a top side with circuitry coupled to bond pads thereon and a back side with a metal (BSM) layer thereon. The semiconductor die is mounted top side up with the BSM layer on the first ring. A metal die attach layer directly contacts the BSM layer, sidewalls of the bottom cavity portion, and a bottom side of the metal substrate.

公开(公告)号：US10832991B1

公开(公告)日：2020-11-10

申请号：US16404958

申请日：2019-05-07

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Nazila Dadvand ,  Sreenivasan Koduri

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  C25D3/38

Abstract: A leadless packaged semiconductor device includes a metal substrate having at least a first through-hole aperture having a first outer ring and a plurality of cuts through the metal substrate to define spaced apart metal pads on at least two sides of the first through-hole aperture. A semiconductor die that has a back side metal (BSM) layer on its bottom side and a top side with circuitry coupled to bond pads is mounted top side up on the first outer ring. A metal die attach layer is directly between the BSM layer and walls of the metal substrate bounding the first through-hole aperture that provides a die attachment that fills a bottom portion of the first through-hole aperture. Bond wires are between metal pads and the bond pads. A mold compound is also provided including between adjacent ones of the metal pads.

公开(公告)号：US10957635B2

公开(公告)日：2021-03-23

申请号：US16359628

申请日：2019-03-20

Applicant: Texas Instruments Incorporated

Inventor： Nazila Dadvand ,  Sreenivasan Koduri ,  Benjamin Stassen Cook

IPC: H01L21/48 ,  H01L21/56 ,  H01L25/18 ,  H01L25/065 ,  C25D7/12 ,  C25D3/38 ,  H01L23/00 ,  H01L23/13 ,  H01L23/14 ,  H01L23/31 ,  H01L23/367 ,  H01L23/495 ,  H01L23/498 ,  H01L23/544

Abstract: A packaged semiconductor device includes a metal substrate having a first and second through-hole aperture having an outer ring, and metal pads around the apertures on dielectric pads. A first and second semiconductor die have a back side metal (BSM) layer on its bottom side are mounted top side up on a top portion of the apertures. A metal die attach layer is directly between the BSM layer and walls of the metal substrate bounding the apertures to provide a die attachment for the first and the second semiconductor die that fills a bottom portion of the apertures. Leads contact the metal pads, wherein the leads include a distal portion that extends beyond the metal substrate. Bondwires are between the metal pads and bond pads on the first and second semiconductor die, and a mold compound provides encapsulation for the packaged semiconductor device.

公开(公告)号：US10892209B2

公开(公告)日：2021-01-12

申请号：US16363468

申请日：2019-03-25

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Nazila Dadvand ,  Sreenivasan Koduri

IPC: H01L23/495 ,  H01L21/48

Abstract: A semiconductor device includes a metal substrate including a through-hole aperture having a multi-size cavity including a larger area first cavity portion above a smaller area second cavity portion that defines a first ring around the second cavity portion, where the first cavity portion is sized with area dimensions to receive a semiconductor die having a top side with circuitry coupled to bond pads thereon and a back side with a metal (BSM) layer thereon. The semiconductor die is mounted top side up with the BSM layer on the first ring. A metal die attach layer directly contacts the BSM layer, sidewalls of the bottom cavity portion, and a bottom side of the metal substrate.

公开(公告)号：US10832993B1

公开(公告)日：2020-11-10

申请号：US16408108

申请日：2019-05-09

Applicant: Texas Instruments Incorporated

Inventor： Nazila Dadvand ,  Sreenivasan Koduri ,  Benjamin Stassen Cook

IPC: H01L23/495 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31

Abstract: A leadless multichip semiconductor device includes a metal substrate having a through-hole aperture with an outer ring for holding a bottom semiconductor die with an inner row and an outer row of metal pads. The bottom semiconductor die has a back side metal (BSM) layer on its bottom side and a top side with bond pads mounted top side up on the ring. A metal die attach layer is directly between the BSM layer and walls of the metal substrate providing a die attachment that fills a bottom portion of the aperture. Bond wires are between the inner metal pads and the bond pads. A top semiconductor die has top bond pads mounted top side up on a dielectric adhesive on the bottom semiconductor die. Pins connect the top bond pads to the outer metal pads. A mold compound provides isolation between adjacent ones of the metal pads.