公开(公告)号：US07477553B2

公开(公告)日：2009-01-13

申请号：US11735429

申请日：2007-04-13

Applicant: Ivan Miro Panades

Inventor： Ivan Miro Panades

IPC: G11C7/00

CPC classification number: G06F5/14 ,  G06F2205/102

Abstract: A control device is provided for controlling a buffer memory that can store n data words and is capable of being used for data transfer between a first system and a second system. The control device includes a write pointer and a read pointer. The control device also includes a write management circuit and a read management circuit. The write management circuit compares the content of the write pointer and the content of the read pointer, and authorizes or does not authorize a write operation in the memory. The read management circuit compares the content of the write pointer and the content of the read pointer, and authorizes or does not authorize a read operation in the memory.

Abstract translation: 提供控制装置用于控制可以存储n个数据字的缓冲存储器，并且能够用于第一系统和第二系统之间的数据传送。 控制装置包括写指针和读指针。 控制装置还包括写入管理电路和读取管理电路。 写入管理电路比较写指针的内容和读指针的内容，并授权或不授权存储器中的写操作。 读取管理电路比较写指针的内容和读指针的内容，并授权或不授权存储器中的读操作。

公开(公告)号：US07474241B2

公开(公告)日：2009-01-06

申请号：US11733375

申请日：2007-04-10

Applicant: Eric Andre

Inventor： Eric Andre

IPC: H03M3/00

CPC classification number: H03M3/464 ,  H03M3/43 ,  H03M3/454

Abstract: An analog-digital delta-sigma converter includes a plurality of continuous time integrators for performing a delta-sigma modulation. Each integrator includes at least one charge sharing integrator at a modulator input. One or more pure integrators follow the charge sharing integrator.

Abstract translation: 模拟数字Δ-Σ转换器包括用于执行Δ-Σ调制的多个连续时间积分器。 每个积分器在调制器输入端包括至少一个电荷共享积分器。 一个或多个纯积分器跟随电荷共享积分器。

公开(公告)号：US20080320161A1

公开(公告)日：2008-12-25

申请号：US12143196

申请日：2008-06-20

Applicant: Giuseppe Maruccia ,  Riccardo Locatelli ,  Lorenzo Pieralisi ,  Marcello Coppola

Inventor： Giuseppe Maruccia ,  Riccardo Locatelli ,  Lorenzo Pieralisi ,  Marcello Coppola

IPC: G06F15/173

CPC classification number: G06F13/28

Abstract: A method is for transferring data from a source target to a destination target in a network. The method includes sending at least one request packet for the destination target, with the request packet containing information relating to a first address where data are located and a second address where data are to be stored. Moreover, at least one transaction request is sent to the source target, with the read request being elaborated from information contained in the request packet. The source target transfers the data located at the first address to the second address.

Abstract translation: 一种方法是将数据从源目标传输到网络中的目标目标。 该方法包括：发送用于目的地目的地的至少一个请求分组，其中该请求分组包含与数据所在的第一地址有关的信息，以及存储数据的第二地址。 此外，至少一个事务请求被发送到源目标，其中读请求是从包含在请求分组中的信息进行阐述的。 源目标将位于第一地址的数据传送到第二个地址。

公开(公告)号：US20080303843A1

公开(公告)日：2008-12-11

申请号：US12133150

申请日：2008-06-04

Applicant: Gilles Ries

Inventor： Gilles Ries

IPC: G09G5/00

CPC classification number: G06T15/80

Abstract: A method generates an image from a set of image zones each delimited by a contour of polygonal shape defined by a set of vertexes, and comprising pixels having an attribute value which can be deduced from the value of a corresponding attribute of each of the vertexes of the image zone. The method includes determining to within a pixel the pixels that belong to each image zone according to the dimensions in number of pixels of the image to be generated; associating the pixels of each image zone in blocks of pixels; and determining an attribute value for each block of pixels of each image zone as a function of the value of the corresponding attribute of each vertex of the image zone.

Abstract translation: 一种方法从一组图像区域生成图像，每个图像区域由一组顶点限定的多边形轮廓界定，并且包括具有属性值的像素，该属性值可以从每个顶点的相应属性的值 图像区域。 该方法包括根据要生成的图像的像素数量的尺寸，在像素内确定属于每个图像区域的像素; 将像素块中的每个图像区域的像素相关联; 以及根据所述图像区域的每个顶点的对应属性的值来确定每个图像区域的每个像素块的属性值。

公开(公告)号：US07460718B2

公开(公告)日：2008-12-02

申请号：US11155391

申请日：2005-06-17

Applicant: Antoine Gautier ,  Mahesh Chandra

Inventor： Antoine Gautier ,  Mahesh Chandra

IPC: G06K9/36

CPC classification number: H04N19/60 ,  H04N19/85 ,  H04N2201/33378

Abstract: The conversion device includes an input for receiving data corresponding to an image to be displayed. The received data is in a JPEG decoder output data format A processor is included for reconstructing and writing the image to be displayed into the image memory, in a display module expected input data format. The bandwidth of the image memory is greater than one byte. The processor is fully hardwired and includes a first logic stage for writing the received data byte by byte into an intermediate memory at chosen addresses such that the written data form a sequence of data in the display module expected input data format, and a second logic stage for reading the written data in the intermediate memory, forming successive packets of read data having a size corresponding to the bandwidth, and successively writing the packets into the image memory at chosen addresses such that the written packets together form all the lines of the image.

Abstract translation: 转换装置包括用于接收与要显示的图像相对应的数据的输入。 接收到的数据是JPEG解码器输出数据格式。 包括处理器，用于以显示模块期望的输入数据格式重建和写入要显示的图像到图像存储器中。 图像存储器的带宽大于一个字节。 处理器是完全硬连线的，并且包括用于逐字地将所接收的数据逐字地写入到所选地址的中间存储器中的第一逻辑级，使得写入的数据形成显示模块预期输入数据格式的数据序列，以及第二逻辑级 用于读取中间存储器中的写入数据，形成具有与带宽相对应的大小的连续的读取数据分组，并且以选定的地址将分组顺序地写入图像存储器，使得所写入的分组一起形成图像的所有行。

公开(公告)号：US07454644B2

公开(公告)日：2008-11-18

申请号：US10480525

申请日：2001-06-15

Applicant: Thierry Giovinazzi ,  Filipe Ganivet

Inventor： Thierry Giovinazzi ,  Filipe Ganivet

IPC: G06F1/04

CPC classification number: G11C7/222 ,  G11C5/066

Abstract: An integrated circuit having a connection terminal for receiving an electric data carrying signal, a circuit for delivering a first clock signal having clock pulses sent after each falling edge of the electric data carrying signal and inside a data sampling window, a circuit for delivering a second clock signal having clock pulses sent only when the electric data carrying signal is at the high level, and a data processing circuit clocked by the second clock signal.

Abstract translation: 一种具有用于接收电数据携带信号的连接端子的集成电路，用于传送具有在电数据传送信号的每个下降沿之后发送的并具有数据采样窗口内的时钟脉冲的第一时钟信号的电路， 时钟信号具有仅当电数据携带信号处于高电平时才发送的时钟脉冲，以及由第二时钟信号定时的数据处理电路。

公开(公告)号：US07447283B2

公开(公告)日：2008-11-04

申请号：US10888088

申请日：2004-07-09

Applicant: Ettore Messina ,  Nicolò Ivan Piazzese ,  Giuseppe Lippolis ,  Elena Salurso ,  Alberto Serratore ,  Agostino Galluzzo

Inventor： Ettore Messina ,  Nicolò Ivan Piazzese ,  Giuseppe Lippolis ,  Elena Salurso ,  Alberto Serratore ,  Agostino Galluzzo

IPC: H04L27/08

CPC classification number: H03G3/3052 ,  H03G3/3036 ,  H03M1/185

Abstract: A method for automatic gain control of an output signal generated from an input signal includes measuring power of the output signal. Measuring power of the output signal includes setting at least one power threshold, measuring a rate of crossing of the at least one power threshold by the output signal over an observation window, and deriving from the rate of crossing a measured power of the output signal. The method further includes providing a reference power, subtracting the measured power from the reference power to obtain an error signal, and mixing the input signal with the error signal. An analog-to-digital conversion is performed on a result of the mixing to obtain a gain-controlled output signal.

Abstract translation: 用于对从输入信号产生的输出信号进行自动增益控制的方法包括测量输出信号的功率。 输出信号的测量功率包括设置至少一个功率阈值，通过观测窗口测量所述至少一个功率阈值与所述输出信号的交叉速率，以及从所述输出信号的测量功率的交叉速率导出。 该方法还包括提供参考功率，从参考功率中减去测量的功率以获得误差信号，以及将输入信号与误差信号混合。 对混合的结果执行模数转换以获得增益控制的输出信号。

公开(公告)号：US07447074B2

公开(公告)日：2008-11-04

申请号：US11481576

申请日：2006-07-05

Applicant: François Jacquet

Inventor： François Jacquet

IPC: G11C11/34

CPC classification number: H01L27/112 ,  G11C7/18 ,  G11C17/12

Abstract: An array of ROM cells, each formed of a transistor having a first drain or source region connected to a bit line connecting several transistors in a first direction, the gates of the different transistors being connected to word lines in a second direction perpendicular to the first one, the array comprising a repetition of an elementary pattern extending over three lines in each direction and comprising nine transistors arranged so that each of the lines of the elementary pattern comprises two cells, two neighboring transistors of each pattern in the first direction sharing a same second region connected to a ground line and being connected to different bit lines from a word line to the other.

Abstract translation: 一种ROM单元阵列，每个由具有第一漏极或源极区域的晶体管形成，该第一漏极或源极区域连接到在第一方向上连接多个晶体管的位线，不同晶体管的栅极沿垂直于第一方向的第二方向连接到字线 一个，该阵列包括在每个方向上三条线上延伸的基本图案的重复，并且包括九个晶体管，其布置成使得基本图案的每条线包括两个单元，在第一方向上的每个图案的两个相邻晶体管共享相同 第二区域连接到地线并且连接到从字线到另一个的不同位线。

公开(公告)号：US20080256332A1

公开(公告)日：2008-10-16

申请号：US11480769

申请日：2006-06-30

Applicant: Didier Fuin

Inventor： Didier Fuin

IPC: G06F9/46

CPC classification number: H03M7/30 ,  G06F8/4434 ,  Y10S707/99942

Abstract: The invention relates to a process for compression of executable code (2) by a microprocessor, comprising steps consisting of decomposing the executable code into words; compressing each word of executable code, each compressed word of executable code comprising a part (BC) of predefined fixed length and a part (VLI) of variable length whereof the length is defined by the part of fixed length; and combining all the parts of fixed length and all the parts of variable length of the words respectively into a block of parts of fixed length and in a block (12) of parts of variable length, the respective positions of at least certain parts of variable length in the block of parts of variable length being saved in an addressing table (13).

Abstract translation: 本发明涉及一种由微处理器压缩可执行代码（2）的过程，包括将可执行代码分解为单词的步骤; 压缩可执行代码的每个字，每个可执行代码的压缩字包括预定义固定长度的部分（BC）和可变长度的部分（VLI），其长度由固定长度的一部分定义; 将所述单词的固定长度的所有部分和所述单词的可变长度的所有部分分别组合成固定长度的部分块和可变长度部分的块（12）中，可变长度的至少一部分的各自位置 可变长度部分块中的长度保存在寻址表（13）中。

公开(公告)号：US20080228989A1

公开(公告)日：2008-09-18

申请号：US11954606

申请日：2007-12-12

Applicant: Frederic Bancel ,  Nicolas Berard ,  David Hely

Inventor： Frederic Bancel ,  Nicolas Berard ,  David Hely

IPC: G06F12/00

CPC classification number: G06F21/79

Abstract: A method reads a datum saved in a memory by selecting an address of the memory in which the datum to be read is saved, reading the datum in the memory at the selected address, saving the datum read in a storage space, and when the memory is not being accessed by a CPU, reading the datum in the memory, reading the datum saved in the storage space, and activating an error signal if the datum read in the memory is different from the datum saved. The method can be applied particularly to the protection of smart card integrated circuits.

Abstract translation: 一种方法是通过选择存储器的地址来读取保存在存储器中的数据，其中要读取的数据被保存在其中，以选定的地址读取存储器中的数据，将数据读入存储空间中，以及当存储器 没有被CPU访问，读取存储器中的数据，读取保存在存储空间中的数据，并且如果在存储器中读取的数据与保存的数据不同，则激活错误信号。 该方法特别适用于智能卡集成电路的保护。