Abstract:
Methods for controlling series or series-parallel reactions are described. Novel microchannel apparatus having mesoporous structures adjacent to bulk flow paths are described. Methods of synthesizing formaldehyde from methanol are also described.
Abstract:
A dynamic floating input D flip-flop (DFIDFF) is provided. The DFIDFF includes a floating input stage, a first string of transistors, and a second string of transistors. At a pre-charge period, the floating input stage transmits the input data to the first string of transistors; the first string of transistors stores the logic status of the input data, and pre-charges its output node to a first level. At an evaluation period, the first string of transistors decides its output node level in accordance with data logic status stored in the first string of transistors; and the second string of transistors decides output level of the D flip-flop in accordance with logic status of the output node of the first string of transistors.
Abstract:
Disclosed is a data search system for searching the data sync pattern by using a physical address or by detecting the falling edge of the blank area end. The data search system comprises a first data start indicator, a second data start indicator, a decision circuit, a window generator and a data sync pattern search circuit. The first data start indicator generates a first start search signal indicating a first start position. The second data start indicator generates a second start search signal indicating a second start position. The decision circuit selects to output one of the start search signals. The window generator generates a window interval starting from the start position. The data sync pattern search circuit searches a data sync pattern of the data in the window interval to determine the data following the data sync pattern.
Abstract:
The present invention discloses an address protection method and circuit capable of efficiently protecting inputting addresses from corruption. The predictable order of a series of original addresses is checked and then the correct addresses are generated by correcting the corrupted addresses within the original addresses. The address protection method and circuit according to the present invention can improve the accuracy of the inputting addresses and increase the validity of data in response to the inputting addresses.
Abstract:
A control circuit and a control method of controlling a rotation frequency of a spindle in an optical disc drive, the control circuit comprising: a spindle controller, electrically coupled to the spindle, for driving the spindle to rotate an optical disc according to a rotation control signal; a detector, electrically coupled to the spindle controller, for detecting the rotation frequency and for generating detecting signals; a frequency-adjusting module, electrically coupled to the detector, for adjusting at least one of the detecting signals to reduce a rotation frequency difference between detecting signals; a signal selector, electrically coupled to the frequency-adjusting module, for receiving output signals generated from the frequency-adjusting module and then outputting the rotation control signal.
Abstract:
A method for fabricating a nitrogen-containing dielectric layer and semiconductor device including the dielectric layer in which a silicon oxide layer is formed on a substrate, such that an interface region resides adjacent to substrate and a surface region resides opposite the interface region. Nitrogen is introduced into the silicon oxide layer by applying a nitrogen plasma. After applying nitrogen plasma, the silicon oxide layer is annealed. The processes of introducing nitrogen into the silicon oxide layer and annealing the silicon oxide layer are repeated to create a bi-modal nitrogen concentration profile in the silicon oxide layer. In the silicon oxide layer, the peak nitrogen concentrations are situated away from the interface region and at least one of the peak nitrogen concentrations is situated in proximity to the surface region. A method for fabricating a semiconductor device is incorporating the nitrogen-containing silicon oxide layers also disclosed.
Abstract:
This invention relates to feed for a hen producing eggs containing DHA, a method for breeding hens and eggs obtained thereby. The feed is mixed with 5 to 200 portions of oil obtained by squeezing Perilla seeds and dregs of the Perilla seeds to be a total of 1,000 portions. After breeding hens with the feed twice a day for more than four successive weeks, eggs containing 0.12% to 0.38% of DHA are obtained. The present invention can provide eggs, which are produced by hens fed with the feed added with oil obtained by squeezing Perilla seeds and with the Perilla seed dregs after being squeezed, highly containing DHA and ALA and has a good health effect compared with the conventional arts and keeping the original taste, lower the costs for breeding, and make the breeding effect better.
Abstract:
A technique for allowing a non-SIP user to call a SIP user includes dialing an established service number that indicates a desire to place a call to a SIP user. The SIP URI of the intended call recipient is included in a call setup protocol message associated with dialing the service number. A non-SIP network recognizes the call to the service number and the SIP URI from the UUI parameter of the call setup message. The call is then routed to a gateway for interfacing between the non-SIP network and the appropriate SIP network where the SIP URI is extracted from the message received by the gateway and used to generate an SIP INVITE message for establishing the call with the intended SIP user.
Abstract:
A method is provided for fabricating a semiconductor device on a semiconductor substrate. A plurality of narrow gate pitch transistors (NPTs) and wide gate pitch transistors (WPTs) are formed on and in the semiconductor substrate. The NPTs are spaced apart by a first distance, and the WPTs are spaced apart by a second distance greater than the first distance. A first stress liner layer is deposited overlying the NPTs, the WPTs and the semiconductor layer, an etch stop layer is deposited overlying the first stress liner layer, and a second stress liner layer is deposited overlying the etch stop layer. A portion of the second stress liner layer which overlies the WPTs is covered, and an exposed portion of the second stress liner layer which overlies the NPTs is removed to expose an exposed portion of the etch stop layer. The exposed portion of the etch stop layer which overlies the NPTs is removed.