公开(公告)号：US12107499B2

公开(公告)日：2024-10-01

申请号：US17661361

申请日：2022-04-29

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Helene Esch ,  Alexandre Meillereux

IPC: H02M3/158

CPC classification number: H02M3/158

Abstract: The present disclosure relates to a switched-mode Power Supply Buck Converter comprising: a switch connected between a node receiving a supply potential and an internal node; another switch connected between the internal node and a node receiving a reference potential; an inductive element coupling the internal node to an output node; and a control circuit controlling the switches so that current pulses in the inductive element have a maximum value selected from among at least a first value and a second value based on an average current drawn at the output node.

公开(公告)号：US20240275335A1

公开(公告)日：2024-08-15

申请号：US18436510

申请日：2024-02-08

Applicant: STMicroetectronics Razoj Polprevodnikov D.O.O ,  STMicroelectronics (Grenoble 2), SAS

Inventor： Tilen Svete ,  Gregoire Montjaux

IPC: H03F1/02 ,  H03F3/19

CPC classification number: H03F1/0233 ,  H03F3/19 ,  H03F2200/105 ,  H03F2200/451

Abstract: A method for controlling an envelope shape of an output signal outputted by a driver of a wireless transmitter includes supplying a first voltage level and a second voltage level, generating a filtered envelope reference signal by switching between the first voltage level and the second voltage level, in conjunction with low-pass filtering the transitions between the first voltage level and the second voltage level, generating a driver supply voltage following the filtered envelope reference signal, regulated in a manner adapted to supply the driver, and controlling the envelope shape of the output signal by supplying the driver with the driver supply voltage.

公开(公告)号：US12056912B2

公开(公告)日：2024-08-06

申请号：US17512080

申请日：2021-10-27

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Shenzhen) R&D Co. Ltd.

Inventor： Etienne Bossart ,  Ji Nan Li ,  Thomas Perotto

IPC: G06K9/00 ,  G01S7/481 ,  G01S17/08 ,  G06V10/50 ,  G06V20/00

CPC classification number: G06V10/507 ,  G01S7/4816 ,  G01S17/08 ,  G06V20/00

Abstract: In an embodiment a method for detecting a presence of at least one object in a field of view of a time of flight sensor includes successively generating, by the time of flight sensor, histograms, each histogram comprising several classes associating a number of photons detected at a given acquisition period, adding several successively generated histograms so as to obtain a summed histogram and analyzing the summed histogram to detect the presence of at least one object in the field of view of the time of flight sensor.

公开(公告)号：US12038801B2

公开(公告)日：2024-07-16

申请号：US18081011

申请日：2022-12-14

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Sylvain Chavagnat ,  Simon Valcin

IPC: G06F1/3234

CPC classification number: G06F1/3243

Abstract: Disclosed herein is a debug system including a host computer, a microcontroller, and a debug probe for interface therebetween for performing debug trace operations. The debug probe samples the current drawn by the microcontroller. The debug probe and host computer cooperate so as to acquire and accurately align trace data and the samples of the current drawn by the microcontroller. Techniques for performing this alignment are described herein and enable for accurate inferences to be drawn about the current drawn by the microcontroller during different program operations.

公开(公告)号：US20240235274A1

公开(公告)日：2024-07-11

申请号：US18403385

申请日：2024-01-03

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics Austria GmbH

Inventor： Bruno Tisserand ,  Oliver Regenfelder ,  Laurent Regnier ,  Martin Rampetsreiter ,  Christoph Chlestil

IPC: H02J50/60 ,  H02J50/20 ,  H02J50/80

CPC classification number: H02J50/60 ,  H02J50/20 ,  H02J50/80

Abstract: The present disclosure relates to an NFC device configured for wireless power transfer, the NFC device comprising an antenna, a frontend circuit coupled to the antenna, a microcontroller coupled to the frontend circuit, the microcontroller comprising an analog-to-digital converter. The analog-to-digital converter is configured to receive an analog amplitude and/or phase signal from the frontend circuit, and to convert the analog signal into a digital signal. The microcontroller is configured to process the digital signal in order to detect a variation in the amplitude and/or phase of the analog signal, so as to detect a change of impedance within the field of the NFC device.

公开(公告)号：US11994537B2

公开(公告)日：2024-05-28

申请号：US17743785

申请日：2022-05-13

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Vratislav Michal

IPC: G01R15/16 ,  G01R19/00

CPC classification number: G01R15/16 ,  G01R19/0084

Abstract: In an embodiment, a circuit includes a first branch coupled between a first node and a second node, the first branch including a first ceramic capacitor, the first ceramic capacitor including terminals configured to receive a first voltage applied therebetween. The circuit further includes a second branch coupled between the first node and a third node, the second branch including a second ceramic capacitor that is substantially identical to the first ceramic capacitor, the second ceramic capacitor including terminals configured to receive a second voltage applied therebetween. The circuit further includes a control circuit configured to modify the second voltage until a first current passing through the second node is substantially equal to a second current passing through the third node.

公开(公告)号：US20240162259A1

公开(公告)日：2024-05-16

申请号：US18388927

申请日：2023-11-13

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Younes BOUTALEB ,  Julien CUZZOCREA

IPC: H01L27/146 ,  H01L23/00

CPC classification number: H01L27/14618 ,  H01L24/48 ,  H01L27/14683 ,  H01L2224/48091 ,  H01L2224/48227

Abstract: A method of fabricating a package for an integrated circuit chip, includes: a) mounting the integrated circuit chip to a support; b) forming a first resist layer over the integrated circuit chip which has a first opening emerging onto a central portion of the integrated circuit chip; c) forming a second resist layer over the first resist layer which has a second opening having a central portion emerging onto the first opening and a peripheral portion emerging onto the first layer; d) arranging a transparent plate in the second opening; and e) forming a third resist layer over the second resist layer and transparent plate which has a third opening emerging onto a central portion of the transparent plate.

公开(公告)号：US20240153553A1

公开(公告)日：2024-05-09

申请号：US18406097

申请日：2024-01-06

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics S.r.l.

Inventor： Antonino Conte ,  Alin Razafindraibe ,  Francesco Tomaiuolo ,  Thibault Mortier

IPC: G11C13/00

CPC classification number: G11C13/0028 ,  G11C13/0004 ,  G11C13/003 ,  G11C2213/79

Abstract: In an embodiment, a non-volatile memory device is proposed. The device includes a plurality of local pull-up stages distributed along a group of memory portions in a memory array. Each local pull-up stage includes, for each wordline that extends through the group of memory portions, a corresponding local pull-up transistor of an NMOS type. The local pull-up transistors of each local pull-up are configured to locally decouple the corresponding wordline from a node at a first reference potential in response to a wordline that extends through the group of memory portions being selected, and locally couple the corresponding wordline to the node at the first reference potential in response to all the wordlines that extend through the group of memory portions being deselected to restore locally a deselection voltage on a wordline previously selected.

公开(公告)号：US11971505B2

公开(公告)日：2024-04-30

申请号：US17107313

申请日：2020-11-30

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Pascal Mellot

IPC: G01S7/4865 ,  G01S7/487 ,  G01S17/10

CPC classification number: G01S7/4865 ,  G01S7/487 ,  G01S17/10

Abstract: A method includes counting a first set of photons having times of flight that falls within a first time range and being detected during a first time period, determining a second time range based on the first set of photons, the second time range being smaller than the first time range, counting a second set of photons having times of flight that fall within the second time range and being detected during a second time period, and determining a third time range based on the second set of photons, the third time range being smaller than the second time range.

公开(公告)号：US20240079363A1

公开(公告)日：2024-03-07

申请号：US18237489

申请日：2023-08-24

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Romain COFFY ,  Younes BOUTALEB

IPC: H01L23/00 ,  H01L23/051 ,  H01L23/31

CPC classification number: H01L24/16 ,  H01L23/051 ,  H01L23/3121 ,  H01L24/08 ,  H01L24/83 ,  H01L2224/08225 ,  H01L2224/16227 ,  H01L2224/81203 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01327 ,  H01L2924/18161 ,  H01L2924/3511

Abstract: An integrated circuit package includes a support substrate and a cover fastened on a first face of the support substrate. The cover and support substrate define a housing containing an electronic integrated circuit chip having a first face equipped with electrically conductive protruding elements. A first space between the cover and a second face of the electronic integrated circuit chip is filled with a first shape memory material in the austenitic state. A second space between each pair of electrically conductive protruding elements and electrically conductive contact pads of the support substrate is filled with a second shape memory material in the austenitic state.