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公开(公告)号：US20240153553A1
公开(公告)日：2024-05-09
申请号：US18406097
申请日：2024-01-06
Inventor： Antonino Conte , Alin Razafindraibe , Francesco Tomaiuolo , Thibault Mortier
IPC: G11C13/00
CPC classification number: G11C13/0028 , G11C13/0004 , G11C13/003 , G11C2213/79
Abstract: In an embodiment, a non-volatile memory device is proposed. The device includes a plurality of local pull-up stages distributed along a group of memory portions in a memory array. Each local pull-up stage includes, for each wordline that extends through the group of memory portions, a corresponding local pull-up transistor of an NMOS type. The local pull-up transistors of each local pull-up are configured to locally decouple the corresponding wordline from a node at a first reference potential in response to a wordline that extends through the group of memory portions being selected, and locally couple the corresponding wordline to the node at the first reference potential in response to all the wordlines that extend through the group of memory portions being deselected to restore locally a deselection voltage on a wordline previously selected.
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公开(公告)号：US20220284954A1
公开(公告)日：2022-09-08
申请号：US17667080
申请日：2022-02-08
Inventor： Antonino Conte , Alin Razafindraibe , Francesco Tomaiuolo , Thibault Mortier
IPC: G11C13/00
Abstract: In an embodiment, a non-volatile memory device includes a memory array including a plurality of memory portions, each memory portion having a respective plurality of memory cells arranged in rows and columns, wherein the memory portions are arranged in groups, each group of memory portions having a plurality of respective memory portions arranged in a row and a plurality of respective wordlines that extend through the respective memory portions, and wherein the memory cells of the memory portions of the group are coupled to the respective wordlines and a row decoder including a pre-decoding stage configured to execute a selection, in which it selects a wordline that extends through a group of memory portions and deselects other wordlines that extend through the group of memory portions, and a subsequent deselection, in which it deselects all the wordlines that extend through the group of memory portions, wherein the row decoder further includes, for each group of memory portions, a shared pull-up stage configured to decouple from or couple to a node at a first reference potential each wordline that extends through the group of memory portions, when the wordline is respectively selected or deselected, so as to impose on each wordline, when deselected, a deselection voltage, a plurality of pull-down stages distributed along the group of memory portions, each pull-down stage being configured to locally couple each wordline that extends through the group of memory portions, when selected, to a node at a second reference potential, so as to impose locally a selection voltage on the wordline, wherein each pull-down stage is further configured to locally decouple from the node at the second reference potential each wordline that extends through the group of memory portions, when deselected; and a number of local pull-up stages distributed along the group of memory portions, each local pull-up stage having, for each wordline that extends through the group of memory portions, a corresponding local pull-up transistor of an NMOS type.
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公开(公告)号：US11908514B2
公开(公告)日：2024-02-20
申请号：US17667080
申请日：2022-02-08
Inventor： Antonino Conte , Alin Razafindraibe , Francesco Tomaiuolo , Thibault Mortier
IPC: G11C13/00
CPC classification number: G11C13/0028 , G11C13/003 , G11C13/0004 , G11C2213/79
Abstract: In an embodiment, a non-volatile memory device includes a memory array including a plurality of memory portions, each memory portion having a respective plurality of memory cells arranged in rows and columns, wherein the memory portions are arranged in groups, each group of memory portions having a plurality of respective memory portions arranged in a row and a plurality of respective wordlines that extend through the respective memory portions, and wherein the memory cells of the memory portions of the group are coupled to the respective wordlines and a row decoder including a pre-decoding stage configured to execute a selection, in which it selects a wordline that extends through a group of memory portions and deselects other wordlines that extend through the group of memory portions, and a subsequent deselection, in which it deselects all the wordlines that extend through the group of memory portions, wherein the row decoder further includes, for each group of memory portions, a shared pull-up stage configured to decouple from or couple to a node at a first reference potential each wordline that extends through the group of memory portions, when the wordline is respectively selected or deselected, so as to impose on each wordline, when deselected, a deselection voltage, a plurality of pull-down stages distributed along the group of memory portions, each pull-down stage being configured to locally couple each wordline that extends through the group of memory portions, when selected, to a node at a second reference potential, so as to impose locally a selection voltage on the wordline, wherein each pull-down stage is further configured to locally decouple from the node at the second reference potential each wordline that extends through the group of memory portions, when deselected; and a number of local pull-up stages distributed along the group of memory portions, each local pull-up stage having, for each wordline that extends through the group of memory portions, a corresponding local pull-up transistor of an NMOS type.
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公开(公告)号：US12198756B2
公开(公告)日：2025-01-14
申请号：US18158232
申请日：2023-01-23
Inventor： Antonino Conte , Francesco La Rosa
Abstract: Unclonable function circuitry includes a plurality of pairs of phase-change memory cells in a virgin state, and sensing circuitry coupled to the plurality of pairs of phase-change memory cells in the virgin state. The sensing circuitry identifies a subset of the plurality of pairs of phase-change memory cells in the virgin state based on a reliability mask. Signs of differences of effective resistance values of the identified subset of the plurality of pairs of phase-change memory cells in the virgin state are sensed by the sensing circuitry. The sensing circuitry generates a string of bits based on the sensed signs of differences in the effective resistance values of the identified subset of the plurality of pairs of phase-change memory cells in the virgin state. Processing circuitry coupled to the unclonable function circuitry, in operation, executes one or more operations using the generated string of bits.
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公开(公告)号：US12107591B2
公开(公告)日：2024-10-01
申请号：US18054333
申请日：2022-11-10
Applicant: STMicroelectronics S.r.l.
Inventor： Agatino Massimo Maccarrone , Antonino Conte , Francesco Tomaiuolo , Michelangelo Pisasale , Marco Ruta
IPC: H03M1/06
CPC classification number: H03M1/0604
Abstract: In accordance with an embodiment, a digital-to-analog converter (DAC) includes: a W-2W current mirror that includes a first plurality of MOS transistors having a first width, and second plurality of MOS transistors having a second width that is twice the first width, where ones of the second plurality of MOS transistors are coupled between drains of adjacent ones of the first plurality of MOS transistors; and a bulk bias generator having a plurality of output nodes coupled to corresponding bulk nodes of the first plurality of MOS transistors, wherein the plurality of output nodes are configured to provide voltages that are inversely proportional to temperature.
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Patent Agency Ranking
公开(公告)号：US11171644B2
公开(公告)日：2021-11-09
申请号：US17207382
申请日：2021-03-19
Inventor： Antonino Conte , Francesco Tomaiuolo , Francesco La Rosa
Abstract: An embodiment power-on-reset circuit, having a power supply input to receive a power supply voltage, generates a reset signal with a value switching upon the power supply voltage crossing a POR detection level. The power-on-reset circuit has: a PTAT stage having a left branch and a right branch and generating a current equilibrium condition between the currents circulating in the left and right branches upon the power supply voltage reaching the POR detection level; and an output stage coupled to the PTAT stage and generating the reset signal, with the value switching at the occurrence of the current equilibrium condition for the PTAT stage. The power-on-reset circuit further comprises a detection-level generation stage, coupled to the PTAT stage as a central branch thereof to define the value of the POR detection level.
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公开(公告)号：US10818368B2
公开(公告)日：2020-10-27
申请号：US16294386
申请日：2019-03-06
Applicant: STMicroelectronics S.r.l.
IPC: G11C8/08 , G11C16/34 , G11C5/14 , G11C16/20 , H03K19/00 , H03K19/0175 , G11C8/06 , G11C13/00 , H03K19/0185 , G11C8/10
Abstract: A level shifter circuit configured to shift an input signal switching within a first voltage range to generate a first output signal correspondingly switching within a second voltage range higher than the first voltage range. The level shifter circuit including a latching core having latching input and output terminals and a supply line configured to be supplied by a supply voltage, and a reference line configured to be coupled to a reference voltage. Capacitive coupling elements are coupled to the latching input and output terminals of the latching core. A driving stage is configured to bias the capacitive coupling elements with biasing signals generated based on the input signal. A decoupling stage is configured to be driven by the driving stage through the capacitive coupling elements to decouple the supply line from the supply voltage and the reference line from the reference voltage during switching of the input signal.
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公开(公告)号：US20190287633A1
公开(公告)日：2019-09-19
申请号：US16294386
申请日：2019-03-06
Applicant: STMicroelectronics S.r.l.
Abstract: A level shifter circuit configured to shift an input signal switching within a first voltage range to generate a first output signal correspondingly switching within a second voltage range higher than the first voltage range. The level shifter circuit including a latching core having latching input and output terminals and a supply line configured to be supplied by a supply voltage, and a reference line configured to be coupled to a reference voltage. Capacitive coupling elements are coupled to the latching input and output terminals of the latching core. A driving stage is configured to bias the capacitive coupling elements with biasing signals generated based on the input signal. A decoupling stage is configured to be driven by the driving stage through the capacitive coupling elements to decouple the supply line from the supply voltage and the reference line from the reference voltage during switching of the input signal.
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公开(公告)号：US20180003761A1
公开(公告)日：2018-01-04
申请号：US15387370
申请日：2016-12-21
Applicant: STMicroelectronics S.r.l. , STMicroelectronics (Crolles 2) SAS , STMicroelectronics (Rousset) SAS
Inventor： Antonino Conte , Enrico Castaldo , Raul Andres Bianchi , Francesco La Rosa
CPC classification number: G01R31/028 , G01R31/2882 , G04F10/10
Abstract: A method can be used for testing a charge-retention circuit for measurement of a time interval having a storage capacitor coupled between a first biasing terminal and a floating node, and a discharge element coupled between the floating node and a reference terminal. The discharge element is configured to implement discharge of a charge stored in the storage capacitor by leakage through a corresponding dielectric. The method includes biasing the floating node at a reading voltage, detecting a biasing value of the reading voltage, implementing an operation of integration of the discharge current in the discharge element with the reading voltage kept constant at the biasing value, and determining an effective resistance value of the discharge element as a function of the operation of integration.
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公开(公告)号：US09413380B2
公开(公告)日：2016-08-09
申请号：US14638246
申请日：2015-03-04
Applicant: STMICROELECTRONICS S.r.l.
Inventor： Antonino Conte , Maria Giaquinta
CPC classification number: G11C16/06 , H03F1/34 , H03F3/347 , H03F3/45 , H03F3/45475 , H03F3/45977 , H03F2200/156 , H03F2200/375 , H03F2200/453 , H03F2203/45101 , H03F2203/45332 , H03F2203/45514 , H03F2203/45546 , H03F2203/45632 , H03M1/661
Abstract: A digital-to-analog converter (DAC) may include a conversion block providing a first analog value. The DAC may also include an amplification block for receiving the first analog value and providing a second analog value amplified by an amplification factor. The amplification block may include a first input terminal for receiving the first analog value, a second input terminal, and an output terminal for providing the second analog value. The amplification block may also include a first capacitive element and a second capacitive element. The first and second capacitive elements may determine the amplification factor. The amplification block may further include a control unit for recovering a charge at a first terminal of the second capacitive element, and based thereon, the second analog value.
Abstract translation: 数模转换器（DAC）可以包括提供第一模拟值的转换块。 DAC还可以包括用于接收第一模拟值并提供由放大因子放大的第二模拟值的放大块。 放大块可以包括用于接收第一模拟值的第一输入端，第二输入端和用于提供第二模拟值的输出端。 放大块还可以包括第一电容元件和第二电容元件。 第一和第二电容元件可以确定放大系数。 放大块还可以包括用于在第二电容元件的第一端子处恢复电荷的控制单元，并且基于该第二模拟值。
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