公开(公告)号：US20220216148A1

公开(公告)日：2022-07-07

申请号：US17702255

申请日：2022-03-23

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Il Goo KIM ,  Roderick A. AUGUR

IPC: H01L23/522 ,  H01L21/768 ,  H01L27/24 ,  H01L27/22

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to top electrode interconnect structures and methods of manufacture. The structure includes: a lower metallization feature; an upper metallization feature; a bottom electrode in direct contact with the lower metallization feature; one or more switching materials over the bottom electrode; a top electrode over the one or more switching materials; and a self-aligned via interconnection in contact with the top electrode and the upper metallization feature.

公开(公告)号：US20220215872A1

公开(公告)日：2022-07-07

申请号：US17143193

申请日：2021-01-07

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vivek Raj ,  Shivraj G. Dharne ,  Uttam K. Saha ,  Mahbub Rashed

IPC: G11C11/419 ,  G11C11/412 ,  H01L27/11

Abstract: A disclosed sense circuit for a memory circuit includes sense amplifiers that detect differences in voltage levels on complementary bitlines during read operations. Instead of the sense amplifiers having built-in footer devices that lead to significant leakage, the sense circuit incorporates a common footer device for all sense amplifiers. To ensure that this footer device has sufficient drive strength to enable voltage differential detection by each sense amplifier, the sense circuit also includes a sense signal generation and boost circuit (SSG&B circuit) that generates a sense mode control signal (SEN) to control the on/off states of the footer device and that further boosts SEN, at the appropriate time, to increase the drive current. By using the common footer device and the SSG&B circuit, leakage from the sense circuit is reduced during a pre-charge operation mode without sacrificing performance during a read operation mode. Also disclosed are associated method embodiments.

公开(公告)号：US11380993B2

公开(公告)日：2022-07-05

申请号：US16720279

申请日：2019-12-19

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Abdellatif Bellaouar

IPC: H01Q5/335 ,  H03F1/08 ,  H04B1/44

Abstract: Disclosed are embodiments of a transceiver front-end configured for a reduced noise figure (NF). Each of the embodiments includes an antenna, a transmitter branch and a receiver branch all connected to an input/output pad. The transmitter branch is coupled to the input/output pad (and thereby the antenna) by an impedance transformer. Only the receiver branch is selectively electrically connected to the input/output pad (and thereby the antenna) by a switch. A common matching network between the input/output pad and the switch provides both impedance matching and electrostatic discharge protection for the switch and the low noise amplifier, thereby reducing NF. Specific embodiments are disclosed for integration into specific technologies (e.g., fully depleted silicon-on-insulator (FDSOI) technology and fin-type field effect transistor (finFET) technology).

公开(公告)号：US20220208599A1

公开(公告)日：2022-06-30

申请号：US17696348

申请日：2022-03-16

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Uzma RANA ,  Anthony K. STAMPER ,  Steven M. SHANK ,  Brett T. CUCCI

IPC: H01L21/76 ,  H01L27/06 ,  H01L21/762 ,  H01L21/26

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to bulk wafer switch isolation structures and methods of manufacture. The structure includes: a bulk substrate material; an active region on the bulk substrate material; an inactive region adjacent to the active region; and an amorphous material covering the bulk substrate material in the inactive region, which is adjacent to the active region.

公开(公告)号：US20220196909A1

公开(公告)日：2022-06-23

申请号：US17131997

申请日：2020-12-23

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Judson R. Holt ,  Yusheng Bian ,  Dali Shao

IPC: G02B6/122 ,  G02B6/12 ,  H01L29/06

Abstract: Disclosed is a silicon-on-insulator (SOI) chip structure with a substrate-embedded optical waveguide. Also disclosed is a method for forming the SOI chip structure. In the method, an optical waveguide is formed within a trench in a bulk substrate prior to a wafer bonding process that results in the SOI structure. Subsequently, front-end-of-the-line (FEOL) processing can be performed to form additional optical devices and/or electronic devices in and/or above the silicon layer. By embedding an optical waveguide within the substrate prior to wafer bonding as opposed to forming it during FEOL processing, strict limitations on the dimensions of the core layer of the optical waveguide are avoided. The core layer of the substrate-embedded optical waveguide can be relatively large such that the cut-off wavelength can be relatively long. Thus, such a substrate-embedded optical waveguide brings different functionality to the SOI chip structure as compared to FEOL optical waveguides.

公开(公告)号：US11368155B1

公开(公告)日：2022-06-21

申请号：US17112456

申请日：2020-12-04

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Dzung T. Tran ,  Shibly S. Ahmed

IPC: H03K19/0175 ,  H03K19/0185 ,  H03K19/20 ,  H03K19/003

Abstract: Embodiments of the disclosure provide an input output (IO) structure in which complimentary nodes of a level shifter are utilized to logically block the output of the IO structure from switching until both power supplies to the IO structure are powered up. An illustrative level shifter includes: a cross-coupled pair of PFETs configured to output complimentary voltage values at a first node and a second node; a control circuit configured to select which of the complementary voltage values are output to the first node and second node; a logic inverter having an input coupled to the first node and an output coupled to a third node; and a NAND gate having inputs coupled to the second node and third node and that generates a level shifted output.

公开(公告)号：US20220190145A1

公开(公告)日：2022-06-16

申请号：US17120916

申请日：2020-12-14

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Sarah McTaggart ,  Qizhi Liu ,  Vibhor Jain ,  Mark Levy ,  Paula Fisher ,  James R. Elliott

IPC: H01L29/737 ,  H01L29/66

Abstract: Device structures and fabrication methods for heterojunction bipolar transistors. Trench isolation regions are positioned in a semiconductor substrate to define active regions. A base layer includes first sections that are respectively positioned over the active regions and second sections that are respectively positioned over the trench isolation regions. Emitter fingers are respectively positioned on the first sections of the base layer. The first sections of the base layer include single-crystal semiconductor material, and the second sections of the base layer include polycrystalline semiconductor material. The second sections of the base layer are spaced in a vertical direction from the trench isolation regions to define a first cavity that extends about a perimeter of the base layer and second cavities that are connected to the first cavity.

公开(公告)号：US11362177B2

公开(公告)日：2022-06-14

申请号：US16774157

申请日：2020-01-28

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Arkadiusz Malinowski ,  Baofu Zhu ,  Frank W. Mont ,  Ali Razavieh ,  Julien Frougier

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/78

Abstract: One illustrative transistor of a first dopant type disclosed herein includes a gate structure positioned above a semiconductor substrate and first and second overall epitaxial cavities formed in the semiconductor substrate on opposite sides of the gate structure. The device also includes a counter-doped epitaxial semiconductor material positioned proximate a bottom of each of the first and second overall epitaxial cavities, wherein the counter-doped epitaxial semiconductor material is doped with a second dopant type that is opposite to the first dopant type, and a same-doped epitaxial semiconductor material positioned in each of the first and second overall epitaxial cavities above the counter-doped epitaxial semiconductor material, wherein the same-doped epitaxial semiconductor material is doped with a dopant of the first dopant type.

公开(公告)号：US11353651B2

公开(公告)日：2022-06-07

申请号：US17087182

申请日：2020-11-02

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Abdelsalam A. Aboketaf ,  Won Suk Lee ,  Yusheng Bian

IPC: G02B6/24 ,  G02B6/028 ,  G02B6/122 ,  G02B6/12

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to multi-mode optical waveguide structures with isolated absorbers and methods of manufacture. The structure includes: a waveguide structure including tapered segments; and at least one isolated waveguide absorber adjacent to the waveguide structure along its length.

公开(公告)号：US11349030B2

公开(公告)日：2022-05-31

申请号：US16739299

申请日：2020-01-10

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Jiehui Shu ,  Haiting Wang ,  Hong Yu

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/66 ,  H01L21/762 ,  H01L21/02

Abstract: A transistor device that includes a single semiconductor structure having an outer perimeter and a vertical height, wherein the single semiconductor structure is at least partially defined by a trench formed in a semiconductor substrate and a first layer of material positioned on the bottom surface of the trench and around the outer perimeter of the single semiconductor structure. The device also includes a second layer of material positioned on the first layer of material and around the outer perimeter of the single semiconductor structure, a gap between the outer perimeter of the single semiconductor structure and both the first and second layers of material (when considered collectively) and an insulating sidewall spacer positioned in the gap, wherein the insulating sidewall spacer has a vertical height that is less than the vertical height of the single semiconductor structure.