公开(公告)号：US20060036881A1

公开(公告)日：2006-02-16

申请号：US11140620

申请日：2005-05-27

Applicant: Mark Homewood

Inventor： Mark Homewood

IPC: G06F1/26

CPC classification number: G06F9/30083 ,  G06F1/3203 ,  G06F1/3237 ,  G06F9/325 ,  Y02D10/128

Abstract: Disclosed in this patent document is a processor circuitry, and a method of operating such processor circuitry, comprising execution circuitry, at least one interrupt controller and an idle monitor, said monitor arranged to determine when said pipeline is idle by detecting an opcode and to determine if said execution circuitry is able to enter the idle state and if so to generate a signal to cause at least the execution circuitry to enter said idle state.

Abstract translation: 在该专利文献中公开了一种处理器电路和操作这种处理器电路的方法，包括执行电路，至少一个中断控制器和空闲监视器，所述监视器被布置成通过检测操作码来确定所述管线何时空闲，并且确定 如果所述执行电路能够进入空闲状态，并且如果是这样，则产生使至少执行电路进入所述空闲状态的信号。

公开(公告)号：US06996513B2

公开(公告)日：2006-02-07

申请号：US09878164

申请日：2001-06-07

Applicant: Peter Bellam

Inventor： Peter Bellam

IPC: G06F17/50

CPC classification number: G06F17/5022 ,  G06F17/5036

Abstract: A method and system for identifying an inaccurate model of a hardware circuit includes the steps of simulating a digital model and an analogue model of the circuit to provide first and second sets of simulation results respectively. For each result in the first and second sets of simulation an integer value is determined which represents that result. The integer values are stored in first and second sets of comparison results respectively and the sets of comparison results are compared. An output signal indicating that at least one of the models is inaccurate is produced if the comparison results contradict.

公开(公告)号：US20060010304A1

公开(公告)日：2006-01-12

申请号：US10922242

申请日：2004-08-19

Applicant: Mark Homewood ,  Paolo Faraboschi

Inventor： Mark Homewood ,  Paolo Faraboschi

IPC: G06F12/00

CPC classification number: G06F9/30043 ,  G06F9/30032 ,  G06F9/30145 ,  G06F12/04

Abstract: A method of loading an unaligned word from a specified unaligned word address in a memory, said unaligned word comprising a plurality of indexed portions crossing a word boundary, the method comprising: loading a first aligned word commencing at an aligned word address rounded from said specified unaligned word address; identifying an index representing the location of the unaligned word address relative to the aligned word address; loading a second aligned word commencing at an aligned word address rounded from a second unaligned word address; and combining indexed portions of the first and second aligned words using the identified index to construct the unaligned word.

Abstract translation: 一种从存储器中指定的未对齐字地址加载未对齐字的方法，所述未对齐字包括与字边界交叉的多个索引部分，所述方法包括：加载从所述指定的四边形对齐的字地址开始的第一对齐字 未对齐的字地址; 识别表示未对齐字地址相对于对齐字地址的位置的索引; 加载从第二未对齐字地址四舍五入的对齐字地址开始的第二对齐字; 并且使用所识别的索引来组合第一和第二对齐字的索引部分以构造未对齐字。

公开(公告)号：US20050273540A1

公开(公告)日：2005-12-08

申请号：US11127049

申请日：2005-05-11

Applicant: Jeremy Whaley

Inventor： Jeremy Whaley

IPC: G06F13/24

CPC classification number: G06F13/24

Abstract: The invention provides an interrupt handling system to process a generated interrupt. At least one input is arranged to provide a predetermined active level, with a detection circuit associated with the input which is selectively configurable to detect either the active level or an inactive level. An interrupt request message causes the detection circuit to be configured to detect the active level, so that an enable logic is caused to generate an interrupt. The invention provides an integrated circuit and a method of generating interrupts using the above system, and a consumer electronic device in the form of a set top box or DVD Read and/or Write device.

Abstract translation: 本发明提供一种用于处理产生的中断的中断处理系统。 至少一个输入被布置成提供预定的有效电平，其中检测电路与输入相关联，其被选择性地配置为检测活动电平或无效电平。 中断请求消息使得检测电路被配置为检测有效电平，使得使能逻辑被产生以产生中断。 本发明提供一种使用上述系统产生中断的集成电路和方法，以及机顶盒或DVD读和/或写装置形式的消费电子设备。

公开(公告)号：US06973592B2

公开(公告)日：2005-12-06

申请号：US09981646

申请日：2001-10-16

Applicant: Anthony Debling

Inventor： Anthony Debling

IPC: G06F11/36 ,  G06F11/00

CPC classification number: G06F11/3656

Abstract: An integrated circuit chip comprising embedded digital processor and an on-chip emulation device coupled to said digital signal processor, said emulation device being operable to control said digital processor and to collect information about the operation of said digital processor, the on-chip emulation device having a communication port for off-chip communication, the chip further comprising an on-chip interface having a first port connected to said communication port of said on-chip emulation device and a second port for connection to a non-proprietary bus wherein said interface is operable to convert between a format suitable for said on-chip emulation device and a format suitable for said non-proprietary bus.

Abstract translation: 一种包括嵌入式数字处理器和耦合到所述数字信号处理器的片上仿真装置的集成电路芯片，所述仿真装置可操作以控制所述数字处理器并且收集关于所述数字处理器，片上仿真装置的操作的信息 具有用于片外通信的通信端口，所述芯片还包括片上接口，其具有连接到所述片上仿真装置的所述通信端口的第一端口和用于连接到非专有总线的第二端口，其中所述接口 可操作以在适合于所述片上仿真设备的格式和适用于所述非专有总线的格式之间进行转换。

公开(公告)号：US06973591B2

公开(公告)日：2005-12-06

申请号：US09981624

申请日：2001-10-16

Applicant: Anthony Debling

Inventor： Anthony Debling

IPC: G06F11/00 ,  G06F11/24 ,  G06F11/26

CPC classification number: G06F11/261

Abstract: A debugging system comprising a host computer system and a target device, said target device having an embedded digital processor on an integrated circuit chip, an on-chip emulation device coupled to said digital processor, the on-chip emulation device being operable to control said digital processor and to collect information about the operation of said digital processor, the on-chip emulation device having a communication port operable to receive information from and emit information to the host computer system wherein said debugging system further comprises an interface on said integrated circuit chip having a first port connected to said communication port of said on-chip emulation device and a second port connected to a universal serial bus, said host computer system having a universal serial bus port connected to said universal serial bus wherein said host computer system comprises a proxy server program for managing the universal serial bus port to enable communication over said universal serial bus, and said host computer further comprises application software in use communicating with the proxy server program and hence via said universal serial bus, with the or each digital processor.

Abstract translation: 一种包括主计算机系统和目标设备的调试系统，所述目标设备在集成电路芯片上具有嵌入式数字处理器，耦合到所述数字处理器的片上仿真设备，所述片上仿真设备可操作以控制所述 数字处理器并且收集关于所述数字处理器的操作的信息，所述片上仿真设备具有可操作以从主机计算机系统接收信息并向其发送信息的通信端口，其中所述调试系统还包括所述集成电路芯片上的接口 具有连接到所述片上仿真装置的所述通信端口的第一端口和连接到通用串行总线的第二端口，所述主计算机系统具有连接到所述通用串行总线的通用串行总线端口，其中所述主计算机系统包括 代理服务器程序，用于管理通用串行总线端口，以实现所述通信 通用串行总线，并且所述主机还包括使用中的应用软件，与代理服务器程序通信，并因此通过所述通用串行总线与所述或每个数字处理器通信。

公开(公告)号：US06972615B2

公开(公告)日：2005-12-06

申请号：US10620834

申请日：2003-07-15

Applicant: Tahir Rashid

Inventor： Tahir Rashid

IPC: G05F3/22 ,  G05F3/30 ,  G05F1/10 ,  G05F3/02

CPC classification number: G05F3/225 ,  G05F3/30

Abstract: The described embodiments of the invention relate to a voltage reference generator which can be produced using new process technologies and which is still compatible with older designs/products. This is achieved by the introduction of circuitry to generate an offset voltage independently of the main reference voltage generation circuitry.

Abstract translation: 所描述的本发明的实施例涉及一种可以使用新的工艺技术制造的并且与旧的设计/产品兼容的电压参考发生器。 这通过引入电路来实现，以产生独立于主参考电压产生电路的偏移电压。

公开(公告)号：US20050231506A1

公开(公告)日：2005-10-20

申请号：US10445295

申请日：2003-05-22

Applicant: Robert Simpson ,  Zahid Hussain

Inventor： Robert Simpson ,  Zahid Hussain

IPC: G06T15/40 ,  G09G5/02 ,  G09G5/36

CPC classification number: G06T15/405

Abstract: A method of rendering a plurality of triangles into a color buffer defined by a plurality of pixel locations, utilizing a triangle identification buffer and a depth buffer. A relatively unique identifier is assigned to each of the triangles to be rendered. Before color and texture mapping, each triangle is depth compared on a per pixel basis. If a pixel of a current triangle is in front of any existing pixel at that point, the current triangles identifier is over-written into a triangle identification buffer. Color texture data is only retrieved for each triangle that appears in the identification buffer once all triangles have been compared.

Abstract translation: 一种利用三角形识别缓冲器和深度缓冲器将多个三角形呈现为由多个像素位置定义的彩色缓冲器的方法。 将相对唯一的标识符分配给要渲染的每个三角形。 在颜色和纹理映射之前，每个三角形是以每像素为基础的深度比较。 如果当前三角形的像素在该点的任何现有像素的前面，则当前三角形标识符被重写成三角形标识缓冲区。 一旦所有三角形都进行了比较，颜色纹理数据才能被检索出出现在识别缓冲区中的每个三角形。

公开(公告)号：US06948095B2

公开(公告)日：2005-09-20

申请号：US09779049

申请日：2001-02-07

Applicant: Mark Phillips

Inventor： Mark Phillips

IPC: G06F11/26 ,  G06F11/36 ,  G06F11/00

CPC classification number: G06F11/3656 ,  G06F11/261

Abstract: A host computer has a file with a subroutine required for operation of an application on a target. The file is dynamically loaded to memory of the target, whereby the file has an entry point at a dynamically-determined location. Data representative of the address of the entry point is stored in memory at a predetermined location.The application is then run on the target, causing the application to determine the entry point, thereby accessing the subroutine and allowing the subroutine to run.

Abstract translation: 主计算机具有在目标上操作应用程序所需的子程序的文件。 该文件被动态地加载到目标的存储器中，由此文件在动态确定的位置具有入口点。 表示入口点的地址的数据被存储在预定位置的存储器中。 然后应用程序在目标上运行，导致应用程序确定入口点，从而访问子例程并允许子程序运行。

公开(公告)号：US06928643B2

公开(公告)日：2005-08-09

申请号：US09978850

申请日：2001-10-16

Applicant: Sean McGoogan ,  Benedict Gaster ,  Richard Shann

Inventor： Sean McGoogan ,  Benedict Gaster ,  Richard Shann

IPC: G06F9/445 ,  G06F9/44

CPC classification number: G06F9/44521

Abstract: A method of forming an executable program from a plurality of object code modules, each object code module comprising section data and relaxation instructions, at least one of said object code modules comprising a library module of predefined section data and relaxation instructions, the executable program to be run on a target processor having a selected endianness, the method comprising in response to a relaxation instruction, loading a library module into temporary storage; retrieving the value of a first variable, said first variable denoting the selected endianness of the target processor; comparing the value of said first variable with the endianness of the section data and relaxation instructions of the library module; in response to the result of the comparing step not being a match, converting the endianness of the section data of the library module to that of said first variable; processing the relaxation instructions and converted section data to form part of the executable program.

Abstract translation: 一种从多个目标代码模块形成可执行程序的方法，每个对象代码模块包括段数据和松弛指令，所述目标代码模块中的至少一个包括预定义的段数据和松弛指令的库模块， 在具有所选择的字节序的目标处理器上运行，该方法响应于松弛指令，将库模块加载到临时存储器中; 检索第一变量的值，所述第一变量表示所选择的目标处理器的字节顺序; 将所述第一变量的值与库模块的段数据和松弛指令的字节比较; 响应于比较步骤的结果不是匹配，将库模块的段数据的字节顺序转换为所述第一变量的字节数据; 处理放松指令和转换段数据以形成可执行程序的一部分。