公开(公告)号：US20060187702A1

公开(公告)日：2006-08-24

申请号：US11343920

申请日：2006-01-30

Applicant: Francois Jacquet

Inventor： Francois Jacquet

IPC: G11C11/00

CPC classification number: G11C11/419 ,  G11C7/02 ,  G11C7/18 ,  G11C2207/002

Abstract: A RAM memory integrated circuit, in particular a SRAM memory integrated circuit, includes a matrix of memory cells that are arranged between two bit lines via two access transistors. The bit lines are intended in one case to be discharged and in the other case to be maintained at a high precharge potential during a read operation. The bit line of each column of the matrix that is intended to be maintained at the high precharge potential is produced in the form of at least two partial bit lines. The memory cells of each column are implanted in the form of groups of cells which are alternately connected to one or the other of the partial bit lines, respectively.

公开(公告)号：US07091633B2

公开(公告)日：2006-08-15

申请号：US10242518

申请日：2002-09-12

Applicant: Thierry Castagnet ,  Olivier Ladiray

Inventor： Thierry Castagnet ,  Olivier Ladiray

IPC: H01H35/00 ,  H02H3/08 ,  H02H9/02 ,  H02H3/00 ,  H02H7/00

CPC classification number: H03K17/94 ,  Y10T307/865

Abstract: A circuit of interface between a logic sensor and a logic input isolation barrier of a processing circuit, including an element of protection against input overvoltages, a current-limiting circuit connected in series between an input terminal and an output terminal of the interface circuit, and a control stage connected in parallel with the galvanic isolation element to be controlled to control the logic states thereof, the control stage inhibiting the operation of the galvanic isolation element if the input current is smaller than a predetermined threshold.

公开(公告)号：US20060176086A1

公开(公告)日：2006-08-10

申请号：US11337818

申请日：2006-01-23

Applicant: Marius Reffay

Inventor： Marius Reffay

IPC: H03K5/153

CPC classification number: G05F3/245

Abstract: A circuit generates a reference voltage that is independent of temperature. The circuit is built on a substrate according to a CMOS technology, and includes a first stage for generating a first current proportional to temperature and a second stage for generating a second current inversely proportional to temperature. These first and second currents are summed in a resistor connected to a voltage distinct from the ground of the first and second stages and formed by the voltage of the substrate on which the circuit is built.

Abstract translation: 电路产生独立于温度的参考电压。 电路根据CMOS技术构建在衬底上，并且包括用于产生与温度成比例的第一电流的第一级和用于产生与温度成反比的第二电流的第二级。 这些第一和第二电流在连接到不同于第一和第二级的地的电压的电阻器中相加，并且由其上构建电路的衬底的电压形成。

公开(公告)号：US20060171598A1

公开(公告)日：2006-08-03

申请号：US11320165

申请日：2005-12-28

Applicant: Fritz Lebowsky ,  Marina Nicolas

Inventor： Fritz Lebowsky ,  Marina Nicolas

IPC: G06K9/36 ,  H04N11/02

CPC classification number: G06T5/002 ,  G06T2207/10016 ,  H04N19/117 ,  H04N19/119 ,  H04N19/14 ,  H04N19/186 ,  H04N19/42 ,  H04N19/86

Abstract: Artifacts of an incident digital image including pixels carrying information are reduced by determining, for certain pixels being considered from the image, displaced pixels. A displaced pixel associated with a pixel being considered is situated at a location that is displaced with respect to the location of the pixel being considered. Substitution information is determined by taking into account the variations between each piece of information carried by pixels situated at locations adjacent to the pixel being considered. The pixel being considered is then selectively replaced by a substitution pixel equal to the displaced pixel or to a combination of the displaced pixel and the pixel being considered, depending on the value of the substitution information.

Abstract translation: 包括携带信息的像素的入射数字图像的伪像通过对于从图像考虑的某些像素确定位移像素来减少。 与被考虑的像素相关联的位移像素位于相对于所考虑的像素的位置移位的位置处。 通过考虑由位于与被考虑的像素相邻的位置处的像素承载的每条信息之间的变化来确定替换信息。 根据取代信息的值，被考虑的像素被选择性地替换为等于被移位的像素的替代像素，或被替换为所考虑的位移像素和像素的组合。

公开(公告)号：US20060160319A1

公开(公告)日：2006-07-20

申请号：US11302971

申请日：2005-12-14

Applicant: Jean-Christophe Giraudin ,  Sebastien Cremer ,  Philippe Delpech

Inventor： Jean-Christophe Giraudin ,  Sebastien Cremer ,  Philippe Delpech

IPC: H01L21/20

CPC classification number: H01L21/32139 ,  H01L21/84 ,  H01L23/5223 ,  H01L27/13 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A manufacturing process for a capacitor in an interconnection layer includes the following stages: Deposit of a first metallic layer (21); Deposit of a first insulator layer (31) on the first metallic layer (21); Deposit of a second metallic layer (41) on the first insulator layer (31); Formation of an upper electrode (4) in the second layer metallic (41); Deposit of a second insulator layer (13) covering the upper electrode (4); Etching of the second insulator layer to form a spacer (14) on this first insulator layer surrounding the upper electrode (4); then Formation of a lower electrode (2) and a dielectric (3) by removal of parts from the first metallic layer and insulator not covered by the upper electrode (4) or the spacer (14); and Formation of an interconnection line (5). This process allows for manufacturing capacitors with an increased performance, in a simplified fashion at lower cost and with an auto-alignment.

Abstract translation: 互连层中的电容器的制造方法包括以下阶段：第一金属层（21）的沉积; 在第一金属层（21）上沉积第一绝缘体层（31）; 在第一绝缘体层（31）上沉积第二金属层（41）; 在第二层金属（41）中形成上电极（4）; 沉积覆盖上电极（4）的第二绝缘体层（13）。 蚀刻第二绝缘体层以在围绕上电极（4）的该第一绝缘体层上形成间隔物（14）; 然后通过从第一金属层和未被上电极（4）或间隔物（14）覆盖的绝缘体去除零件来形成下电极（2）和电介质（3）; 和互连线（5）的形成。 该过程允许以更低的成本和自动对准以简化的方式制造具有增加的性能的电容器。

公开(公告)号：US20060157820A1

公开(公告)日：2006-07-20

申请号：US11298910

申请日：2005-12-09

Applicant: Guillaume Bouche ,  Jean-Christophe Giraudin

Inventor： Guillaume Bouche ,  Jean-Christophe Giraudin

IPC: H01L29/00

CPC classification number: H01L28/91 ,  H01L27/0805 ,  H01L27/10861 ,  H01L29/66181

Abstract: A process for producing a capacitor integrated into an electronic circuit comprises the formation of a trench in a substrate through a conductive portion similar to an MOS transistor gate. Alternating conductive, insulating and conductive layers are deposited inside the trench T in order to form a lower electrode, a dielectric and an upper electrode of the capacitor, respectively. The conductive portion is used to electrically connect the lower electrode to other electronic components of the circuit without an additional cost with respect to the connection of the circuit transistors.

Abstract translation: 一种集成到电子电路中的电容器的制造方法包括通过类似于MOS晶体管栅极的导电部分在衬底中形成沟槽。 交替的导电，绝缘和导电层沉积在沟槽T的内部，以分别形成电容器的下电极，电介质和上电极。 导电部分用于将下电极与电路的其它电子部件电连接，而不会对电路晶体管的连接造成额外的成本。

公开(公告)号：US07079448B2

公开(公告)日：2006-07-18

申请号：US10867381

申请日：2004-06-14

Applicant: Bruno Leconte ,  Paola Cavaleri ,  Sébastien Zink

Inventor： Bruno Leconte ,  Paola Cavaleri ,  Sébastien Zink

IPC: G11C13/04 ,  G11C16/04

CPC classification number: G11C16/10

Abstract: The present invention relates to a memory in integrated circuit comprising a central Flash-type memory comprising memory cells forming pages, a buffer memory capable of storing binary words, and a sequencer for executing an instruction for saving, in a target page of the Flash memory, a series of external words received at an input terminal of the memory. According to the present invention, the sequencer is arranged for, after saving the series of external words in the buffer memory, saving, in the buffer memory, internal words present in the target page and corresponding, due to their address in the page, to locations of words in the buffer memory that have not received any external words, then erasing the target page and saving in the erased page the words present in the buffer memory.

Abstract translation: 本发明涉及一种集成电路中的存储器，包括一个中央闪存型存储器，包括形成页面的存储单元，能够存储二进制字的缓冲存储器，以及用于执行用于保存在Flash存储器的目标页面中的指令的定序器 ，在存储器的输入端接收的一系列外部字。 根据本发明，定序器被设置为在将一系列外部字保存在缓冲存储器中之后，在缓冲存储器中保存存在于目标页面中并由于其在页面中的地址而对应的内部单词到 在缓冲存储器中没有接收到任何外部字的单词的位置，然后擦除目标页面并保存在擦除的页面中存在于缓冲存储器中的单词。

公开(公告)号：US07071636B2

公开(公告)日：2006-07-04

申请号：US10423659

申请日：2003-04-25

Applicant: Jean-Michel Moreau

Inventor： Jean-Michel Moreau

IPC: H01J29/72

CPC classification number: H04N3/223

Abstract: The invention concerns a control circuit for an electron tube display comprising a deflection coil, the deflection coil being part of a scanning circuit and being coupled to a coil of a transformer powering a high voltage generator used to accelerate an electron beam, a phase locked loop being used to keep in phase the flyback pulses produced by the scanning circuit and the video signal synchronisation pulses, and comprising an electron beam current measuring circuit, a compensation circuit for compensating the phase difference between the flyback pulses and the video signal synchronisation pulses as a function of the measured current.

Abstract translation: 本发明涉及一种用于电子管显示器的控制电路，该电子管显示器包括偏转线圈，该偏转线圈是扫描电路的一部分，并且耦合到用于加速电子束的高压发生器的变压器的线圈，锁相环 用于保持由扫描电路产生的反激脉冲和视频信号同步脉冲，并且包括电子束电流测量电路，用于补偿回扫脉冲和视频信号同步脉冲之间的相位差的补偿电路，作为 测量电流的功能。

公开(公告)号：US20060141339A1

公开(公告)日：2006-06-29

申请号：US11317436

申请日：2005-12-22

Applicant: Mathieu Roy ,  Fabien Pierre

Inventor： Mathieu Roy ,  Fabien Pierre

IPC: H01M4/96 ,  H01M4/88 ,  B32B3/10 ,  B32B3/06

CPC classification number: B82Y30/00 ,  H01L21/76898 ,  H01L2221/1094 ,  H01M4/926 ,  H01M8/0234 ,  H01M8/1007 ,  H01M8/1097 ,  Y02P70/56 ,  Y10T428/24273 ,  Y10T428/249955 ,  Y10T428/249975

Abstract: A thin wafer comprising through holes filled at least partially with conductive carbon nanotubes generally oriented transversally to the wafer. A fuel cell comprising, in a thin wafer, a through hole filled with an electrolyte surrounded with barriers of carbon nanotubes generally oriented transversally to the wafer.

Abstract translation: 包括至少部分地填充有通常横向于晶片定向的导电碳纳米管的通孔的薄晶片。 一种燃料电池，其在薄晶片中包括填充有电解质的通孔，所述电解质围绕着通常横向于所述晶片的碳纳米管的屏障。

公开(公告)号：US07065056B2

公开(公告)日：2006-06-20

申请号：US09896827

申请日：2001-06-29

Applicant: William Glass

Inventor： William Glass

IPC: H04B3/20

CPC classification number: H04B3/238

Abstract: A circuit for transmitting and receiving communications. The circuit includes a transmit block, a receive block, and an echo canceller, coupled to the transmit block and to the receive block, for determining an echo signal and subtracting it from the received signal, the determination of the echo signal involving a predetermined number N of coefficients calculated at the beginning of each of the communications in an initialization phase. The circuit periodically updates during communication a restricted group of coefficients chosen from among the most significant coefficients. The present invention also relates to an echo cancellation method.