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    MIM CAPACITOR
    3.
    发明申请
    MIM CAPACITOR 有权
    MIM电容器

    公开(公告)号：US20070275536A1

    公开(公告)日：2007-11-29

    申请号：US11746177

    申请日：2007-05-09

    Applicant: Sebastien Cremer ,  Cedric Perrot ,  Claire Richard

    Inventor： Sebastien Cremer ,  Cedric Perrot ,  Claire Richard

    IPC: H01L21/20

    CPC classification number: H01L28/91 ,  H01L27/10829

    Abstract: A method for forming a MIM-type capacitor by filling of trenches by conformal depositions of insulating materials and of conductive materials, two successive electrodes of the capacitor including on either side of a thin vertical insulating layer at least one conductive layer of same nature, including the step of lowering the level of the conductive layers with respect to the level of the insulating layer separating them.

    Abstract translation: 一种用于通过绝缘材料和导电材料的共形沉积填充沟槽来形成MIM型电容器的方法，所述电容器的两个连续电极包括在薄垂直绝缘层的至少一个相同性质的导电层的任一侧上，包括 相对于分离它们的绝缘层的水平降低导电层的水平的步骤。

    Method of fabricating a capacitor by using a metallic deposit in an interconnection dielectric layer of an integrated circuit
    5.
    发明申请
    Method of fabricating a capacitor by using a metallic deposit in an interconnection dielectric layer of an integrated circuit 有权
    通过在集成电路的互连电介质层中使用金属沉积物来制造电容器的方法

    公开(公告)号：US20060160319A1

    公开(公告)日：2006-07-20

    申请号：US11302971

    申请日：2005-12-14

    Applicant: Jean-Christophe Giraudin ,  Sebastien Cremer ,  Philippe Delpech

    Inventor： Jean-Christophe Giraudin ,  Sebastien Cremer ,  Philippe Delpech

    IPC: H01L21/20

    CPC classification number: H01L21/32139 ,  H01L21/84 ,  H01L23/5223 ,  H01L27/13 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    Abstract: A manufacturing process for a capacitor in an interconnection layer includes the following stages: Deposit of a first metallic layer (21); Deposit of a first insulator layer (31) on the first metallic layer (21); Deposit of a second metallic layer (41) on the first insulator layer (31); Formation of an upper electrode (4) in the second layer metallic (41); Deposit of a second insulator layer (13) covering the upper electrode (4); Etching of the second insulator layer to form a spacer (14) on this first insulator layer surrounding the upper electrode (4); then Formation of a lower electrode (2) and a dielectric (3) by removal of parts from the first metallic layer and insulator not covered by the upper electrode (4) or the spacer (14); and Formation of an interconnection line (5). This process allows for manufacturing capacitors with an increased performance, in a simplified fashion at lower cost and with an auto-alignment.

    Abstract translation: 互连层中的电容器的制造方法包括以下阶段：第一金属层（21）的沉积; 在第一金属层（21）上沉积第一绝缘体层（31）; 在第一绝缘体层（31）上沉积第二金属层（41）; 在第二层金属（41）中形成上电极（4）; 沉积覆盖上电极（4）的第二绝缘体层（13）。 蚀刻第二绝缘体层以在围绕上电极（4）的该第一绝缘体层上形成间隔物（14）; 然后通过从第一金属层和未被上电极（4）或间隔物（14）覆盖的绝缘体去除零件来形成下电极（2）和电介质（3）; 和互连线（5）的形成。 该过程允许以更低的成本和自动对准以简化的方式制造具有增加的性能的电容器。

    Process for producing an integrated electronic circuit that includes a capacitor
    6.
    发明授权
    Process for producing an integrated electronic circuit that includes a capacitor 有权
    一种包括电容器的集成电子电路的制造方法

    公开(公告)号：US07033887B2

    公开(公告)日：2006-04-25

    申请号：US10850042

    申请日：2004-05-20

    Applicant: Philippe Delpech ,  Christophe Regnier ,  Sebastien Cremer

    Inventor： Philippe Delpech ,  Christophe Regnier ,  Sebastien Cremer

    IPC: H01L21/8242

    CPC classification number: H01L28/60

    Abstract: A process for producing an integrated electronic circuit that includes a capacitor comprises the formation of a stack on top of a substrate (100, 101). The stack comprises a first volume of a temporary material, a second volume (2) of at least one insulating dielectric and a third volume (3) of a first electrically conducting material. After a coating material (4) has been deposited on the stack, the temporary material is removed via access shafts (C1, C2) that are formed between a surface (S) of the circuit and the first volume. The temporary material is then replaced with a second, electrically conducting material.

    Abstract translation: 一种用于制造包括电容器的集成电子电路的方法包括在衬底（100,101）的顶部上形成叠层。 堆叠包括第一体积的临时材料，至少一个绝缘电介质的第二体积（2）和第一导电材料的第三体积（3）。 在涂层材料（4）已经沉积在堆叠上之后，临时材料通过形成在电路的表面（S）和第一体积之间的存取轴（C 1，C 2）去除。 然后用第二导电材料代替临时材料。

    Process for producing an integrated electronic circuit that includes a capacitor
    7.
    发明申请
    Process for producing an integrated electronic circuit that includes a capacitor 有权
    一种包括电容器的集成电子电路的制造方法

    公开(公告)号：US20050032303A1

    公开(公告)日：2005-02-10

    申请号：US10850042

    申请日：2004-05-20

    Applicant: Philippe Delpech ,  Christophe Regnier ,  Sebastien Cremer

    Inventor： Philippe Delpech ,  Christophe Regnier ,  Sebastien Cremer

    IPC: H01L21/02 ,  H01L29/92 ,  H01L21/8234

    CPC classification number: H01L28/60

    Abstract: A process for producing an integrated electronic circuit that includes a capacitor comprises the formation of a stack on top of a substrate (100, 101). The stack comprises a first volume of a temporary material, a second volume (2) of at least one insulating dielectric and a third volume (3) of a first electrically conducting material. After a coating material (4) has been deposited on the stack, the temporary material is removed via access shafts (C1, C2) that are formed between a surface (S) of the circuit and the first volume. The temporary material is then replaced with a second, electrically conducting material.

    Abstract translation: 一种用于制造包括电容器的集成电子电路的方法包括在衬底（100,101）的顶部上形成叠层。 堆叠包括第一体积的临时材料，至少一个绝缘电介质的第二体积（2）和第一导电材料的第三体积（3）。 在涂层材料（4）已经沉积在堆叠上之后，临时材料通过形成在电路的表面（S）和第一体积之间的接近轴（C1，C2）去除。 然后用第二导电材料代替临时材料。

    Process for producing an integrated electronic circuit comprising superposed components and integrated electronic circuit thus obtained
    8.
    发明授权
    Process for producing an integrated electronic circuit comprising superposed components and integrated electronic circuit thus obtained 有权
    一种集成电子电路的制造方法，包括由此获得的重叠部件和集成电子电路

    公开(公告)号：US07202137B2

    公开(公告)日：2007-04-10

    申请号：US10850040

    申请日：2004-05-20

    Applicant: Philippe Delpech ,  Christophe Regnier ,  Sebastien Cremer ,  Stephane Monfray

    Inventor： Philippe Delpech ,  Christophe Regnier ,  Sebastien Cremer ,  Stephane Monfray

    IPC: H01L21/20

    CPC classification number: H01L28/40 ,  H01L21/76264 ,  H01L29/66772 ,  H01L29/78648

    Abstract: A process for producing an integrated electronic circuit. The process begins with the production of a first electronic component and a second electronic component that are superposed on top of a substrate. A volume of temporary material is formed on the substrate at the position of the second electronic component. The first electronic component is then produced above the volume of temporary material relative to the substrate, and then the second electronic component is produced using at least one shaft for access to the temporary material. The first electronic component may be an active component and the second electronic component may be a passive component.

    Abstract translation: 一种集成电子电路的制造方法。 该过程开始于重叠在基板顶部上的第一电子部件和第二电子部件的制造。 在第二电子部件的位置处，在基板上形成一定量的临时材料。 然后在临时材料的体积上方相对于基板制造第一电子部件，然后使用至少一个轴来制造第二电子部件，用于接近临时材料。 第一电子部件可以是有源部件，第二电子部件可以是无源部件。

    CREATION OF CAPACITORS EQUIPPED WITH MEANS TO REDUCE THE STRESSES IN THE METAL MATERIAL OF THEIR LOWER STRUCTURES
    9.
    发明申请
    CREATION OF CAPACITORS EQUIPPED WITH MEANS TO REDUCE THE STRESSES IN THE METAL MATERIAL OF THEIR LOWER STRUCTURES 有权
    具有减少其结构的金属材料应力的手段的电容器的创建

    公开(公告)号：US20090040684A1

    公开(公告)日：2009-02-12

    申请号：US12134490

    申请日：2008-06-06

    Applicant: Sebastien Cremer ,  Philippe Delpech ,  Sylvie Bruyere

    Inventor： Sebastien Cremer ,  Philippe Delpech ,  Sylvie Bruyere

    IPC: H01G4/30 ,  H01G9/00

    CPC classification number: H01L28/87 ,  H01L28/91 ,  Y10T29/417

    Abstract: The method for forming the microelectronic device having at least one two or three dimensional capacitor includes creating, on a substrate, a plurality of components and a number of superimposed metal interconnection levels. An insulating layer is formed above a metal interconnection level, and a horizontal metal zone of a next metal interconnection level in which one or more of the insulating blocks created from this insulating layer are incorporated is formed therein. The zone is designed to form a lower structural part of the capacitor.

    Abstract translation: 用于形成具有至少一个二维或三维电容器的微电子器件的方法包括在衬底上产生多个部件和多个叠加的金属互连电平。 在金属互连层上形成绝缘层，在其中形成有一个或多个由该绝缘层形成的绝缘块的下一个金属互连层的水平金属区。 该区域被设计成形成电容器的下部结构部分。

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