公开(公告)号：US20250013233A1

公开(公告)日：2025-01-09

申请号：US18891741

申请日：2024-09-20

Applicant: Intel Corporation

Inventor： Igor Tatourian ,  Hassnaa Moustafa ,  David John Zage

IPC: G05D1/00 ,  B25J9/16 ,  B60W30/09

Abstract: Apparatuses, storage media and methods associated with cognitive robot systems, such as ADAS for CAD vehicles, are disclosed herein. In some embodiments, an apparatus includes emotional circuitry to receive stimuli for a robot integrally having the robotic system, process the received stimuli to identify potential adversities, and output information describing the identified potential adversities; and thinking circuitry to receive the information describing the identified potential adversities, process the received information describing the identified potential adversities to determine respective fear levels for the identified potential adversities in view of a current context of the robot, and generate commands to the robot to respond to the identified potential adversities, based at least in part on the determined fear levels for the identified potential adversities. Other embodiments are also described and claimed.

公开(公告)号：US12192464B2

公开(公告)日：2025-01-07

申请号：US18018182

申请日：2020-08-27

Applicant: INTEL CORPORATION

Inventor： Vasily Aristarkhov

IPC: H04N7/12 ,  H04N19/127 ,  H04N19/423 ,  H04N19/436

Abstract: A multi-adapter encoding process where the first adapter is used to execute a look-ahead encoding process while the second adapter is used to execute a main encoding process is provided. The look-ahead encode and main encode can be executed concurrently on the different adapters. Additionally, the first adapter can execute the look-ahead encoding process without feedback from the second adapter, or the main encoding process.

公开(公告)号：US12191871B2

公开(公告)日：2025-01-07

申请号：US17355217

申请日：2021-06-23

Applicant: Intel Corporation

Inventor： Evgeny Shumaker ,  Elan Banin ,  Ofir Degani ,  Gil Horovitz

IPC: H03L7/24 ,  G04F10/00 ,  H03L7/085 ,  H03L7/099

Abstract: A TDC circuit configured to receive a reference clock (REF) signal and a signal derived from a LO; generate a plurality of digital values indicative of a measured phase difference between the signal derived from the LO and the REF signal, wherein each of the plurality of digital values are determined from a unique set of a plurality of sets of TDC measurement component quantization levels; generate a combined series of quantization levels based on a combination of the plurality of sets of TDC measurement component quantization levels; and determine a combined digital value from the combined series of quantization levels and at least one of the plurality of digital values to generate an output of the TDC circuit. The combined series of quantization levels may be generated by summing simultaneously occurring levels of each of the plurality of sets of TDC measurement component quantization levels together.

公开(公告)号：US12191230B2

公开(公告)日：2025-01-07

申请号：US17213347

申请日：2021-03-26

Applicant: Intel Corporation

Inventor： Ralph W. Jensen ,  Michael Thomas Crocker ,  Wesley B. Morgan

IPC: H01L23/433 ,  H01L25/18

Abstract: Techniques for liquid cooling systems are disclosed. In one embodiment, jet holes in a water block create jets of liquid coolant to be applied to a surface to be cooled, such as a surface of an integrated circuit component. The jets of liquid coolant may disrupt surface boundary layers through turbulence and/or microcavitation, increasing the cooling effect of the liquid coolant. In the illustrative embodiment, negative pressure is applied to a coolant loop of the liquid coolant, which provides several advantages such as being resistant to leaks. In another embodiments, jet holes in a water block create jets of liquid coolant that are directed toward other jets of liquid coolant, which also increases the cooling effect of the liquid coolant.

公开(公告)号：US12190406B2

公开(公告)日：2025-01-07

申请号：US17359528

申请日：2021-06-26

Applicant: Intel Corporation

Inventor： Raghavendra Kamath Miyar ,  Rajalakshmi Athimoolam ,  Subramaniam Maiyuran ,  Jorge F. Garcia Pabon ,  Rajarshi Bajpayee ,  Krishan Malik

IPC: G06T1/60 ,  G06T1/20

Abstract: Examples described herein relate to an apparatus comprising: at least one memory and at least one processor. In some example, the at least one processor is to: represent at least one vertex in a set of vertices of a first polygon using a first index; store the first index into the at least one memory; and indicate whether the first index is to be de-referenced based on a comparison between the first index and at least one other index, wherein: a first memory pointer is associated with the at least one vertex in the set of vertices of the first polygon and the first index comprises a number of bits that is less than a number of bits associated with the first memory pointer. In some examples, the number of bits of the first index is based on a size of a vertex window and wherein the vertex window comprises multiple vertices associated with one or more draw calls. In some examples, the number of bits of the first index is N and 2N is a size of a vertex window and wherein the vertex window comprises 2N vertices associated with one or more draw calls.

公开(公告)号：US12190114B2

公开(公告)日：2025-01-07

申请号：US17130016

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Niranjan Kumar Soundararajan ,  Sreenivas Subramoney ,  Sr Swamy Saranam Chongala

IPC: G06F9/38

Abstract: In one embodiment, a processor includes a branch predictor to predict whether a branch instruction is to be taken and a branch target buffer (BTB) coupled to the branch predictor. The branch target buffer may be segmented into a first cache portion and a second cache portion, where, in response to an indication that the branch is to be taken, the BTB is to access an entry in one of the first cache portion and the second cache portion based at least in part on a type of the branch instruction, an occurrence frequency of the branch instruction, and spatial information regarding a distance between a target address of a target of the branch instruction and an address of the branch instruction. Other embodiments are described and claimed.

公开(公告)号：US12190012B2

公开(公告)日：2025-01-07

申请号：US17482070

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Aruni Nelson ,  Adeel Aslam ,  Abdul Ismail ,  Devon Worrell ,  Binu John

IPC: G06F3/16

Abstract: Example apparatus disclosed herein compare one or more audio latency characteristics with one or more audio latency requirements in response to detection of an audio silence event, the audio latency characteristic(s) associated with at least one of a hardware layer or a device layer of an audio stack of a compute device, the audio latency requirement(s) associated with an application. Disclosed example apparatus also control a device layer of the audio stack to enter a device layer low power mode in response to a first determination that the audio latency requirement(s) is/are met by the audio latency characteristic(s). Disclosed example apparatus further control a hardware layer of the audio stack to enter a hardware layer low power mode in response to the first determination and a second determination that an operation condition for entry into the hardware layer low power mode is met.

公开(公告)号：US12189792B2

公开(公告)日：2025-01-07

申请号：US17033748

申请日：2020-09-26

Applicant: Intel Corporation

Inventor： Barry E. Huntley ,  Hormuzd M. Khosravi ,  Thomas Toll ,  Ramya Jayaram Masti ,  Siddhartha Chhabra ,  Vincent Von Bokern

IPC: G06F21/60 ,  G06F12/06 ,  H04L9/14

Abstract: Embodiments of apparatuses, methods, and systems for scalable multi-key memory encryption are disclosed. In an embodiment, an apparatus includes a core, an encryption unit, and key identification hardware. The core is to write data to and read data from memory regions, each to be identified by a corresponding address. The encryption unit to encrypt data to be written and decrypt data to be read. The key identification hardware is to use a portion of the corresponding address to look up a corresponding key identifier in a key information data structure. The corresponding key identifier is one multiple key identifiers. The corresponding key identifier is to identify which one of multiple encryption keys is to be used to encrypt and decrypt the data.

公开(公告)号：US12189775B2

公开(公告)日：2025-01-07

申请号：US17725876

申请日：2022-04-21

Applicant: Intel Corporation

Inventor： Ned M. Smith ,  Andrew Draper ,  Xiaoyu Ruan

IPC: G06F21/57

Abstract: An apparatus is disclosed. The apparatus comprises one or more processors to receive a request to perform a firmware update at a device, prepare a second trusted compute base (TCB) layer for the firmware update, generate a first compound device identifier (CDI) associated with a first TCB layer to be used by the second TCB layer to attest an operational state of the first TCB layer prior to applying the update and generate a second CDI associated with the first TCB layer to be used by the second TCB layer to attest the operational state of the first layer after the update has been applied and perform the firmware update of the second TCB layer.

公开(公告)号：US12189452B2

公开(公告)日：2025-01-07

申请号：US17129465

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Kristoffer Fleming ,  Melanie Daniels ,  Paul Diefenbaugh ,  Aleksander Magi ,  Lawrence Falkenstein ,  Raoul Rivas Toledano ,  Vishal Sinha ,  Deepak Samuel Kirubakaran ,  Venkateshan Udhayan ,  Marko Bartscherer ,  Kathy Bui

IPC: G06F1/3231 ,  G06F1/3234 ,  G06N20/00 ,  G06V40/10 ,  G10L15/18 ,  G10L15/22 ,  G10L15/30 ,  H04N23/65 ,  H04W52/02 ,  G10L15/08

Abstract: Methods and apparatus to improve user experience on computing devices are disclosed. An example computing device includes an image sensor. The example computing device further includes wireless communication circuitry. The example computing device also includes an operations controller to cause the wireless communication circuitry to switch between different operation modes based on an analysis of image data generated by the image sensor. Different ones of the operation modes to consume different amounts of power.