公开(公告)号：US20080242012A1

公开(公告)日：2008-10-02

申请号：US11729188

申请日：2007-03-28

Applicant: Sangwoo Pae ,  Jose Maiz ,  Gilbert Dewey ,  Matthew V. Metz ,  Markus Kuhn ,  Mark Doczy ,  Jack Kavalieros

Inventor： Sangwoo Pae ,  Jose Maiz ,  Gilbert Dewey ,  Matthew V. Metz ,  Markus Kuhn ,  Mark Doczy ,  Jack Kavalieros

IPC: H01L21/8234 ,  H01L21/336

CPC classification number: H01L29/517 ,  H01L21/28079 ,  H01L21/28194 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method for fabricating a high quality silicon oxynitride layer for a high-k/metal gate transistor comprises depositing a high-k dielectric layer on a substrate, depositing a barrier layer on the high-k dielectric layer, wherein the barrier layer includes at least one of nitrogen or oxygen, depositing a capping layer on the barrier layer, and annealing the substrate at a temperature that causes at least a portion of the nitrogen and/or oxygen in the barrier layer to diffuse to an interface between the high-k dielectric layer and the substrate. The diffused nitrogen or oxygen forms a high-quality silicon oxynitride layer at the interface. The high-k dielectric layer, the barrier layer, and the capping layer may then be etched to form a gate stack for use in a high-k/metal gate transistor. The capping layer may be replaced with a metal gate electrode using a replacement metal gate process.

Abstract translation: 制造用于高k /金属栅极晶体管的高质量氮氧化硅层的方法包括在衬底上沉积高k电介质层，在高k电介质层上沉积阻挡层，其中阻挡层至少包括 氮气或氧气中的一种，在阻挡层上沉积覆盖层，并且在使阻挡层中的氮和/或氧的至少一部分扩散到高k电介质 层和基底。 扩散的氮或氧在界面处形成高质量的氮氧化硅层。 然后可以蚀刻高k电介质层，阻挡层和覆盖层以形成用于高k /金属栅极晶体管的栅极堆叠。 使用替代金属浇口工艺可以用金属栅电极代替覆盖层。

公开(公告)号：US07422971B2

公开(公告)日：2008-09-09

申请号：US11204418

申请日：2005-08-15

Applicant: Anand Murthy ,  Brian Doyle ,  Jack Kavalieros ,  Robert Chau

Inventor： Anand Murthy ,  Brian Doyle ,  Jack Kavalieros ,  Robert Chau

IPC: H01L21/00

CPC classification number: H01L29/41733 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78618

Abstract: The invention relates to a transistor that includes an ultra-thin body epitaxial layer that forms an embedded junction with a channel that has a length dictated by an undercut under the gate stack for the transistor. The invention also relates to a process of forming the transistor and to a system that incorporates the transistor.

Abstract translation: 本发明涉及一种晶体管，其包括超薄体外延层，该超薄体外延层与具有由晶体管的栅极堆叠下方的底切指定的沟道的沟道形成嵌入的结。 本发明还涉及一种形成晶体管的方法和涉及晶体管的系统。

公开(公告)号：US20080188041A1

公开(公告)日：2008-08-07

申请号：US12079587

申请日：2008-03-26

Applicant: Suman Datta ,  Justin K. Brask ,  Jack Kavalieros ,  Brian S. Doyle ,  Gilbert Dewey ,  Mark L. Doczy ,  Robert S. Chau

Inventor： Suman Datta ,  Justin K. Brask ,  Jack Kavalieros ,  Brian S. Doyle ,  Gilbert Dewey ,  Mark L. Doczy ,  Robert S. Chau

IPC: H01L21/336

CPC classification number: H01L29/42376 ,  H01L21/28114 ,  H01L29/42384 ,  H01L29/495 ,  H01L29/517 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78654

Abstract: Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer, source/drain extensions a distance beneath the metal gate, and lateral undercuts in the sides of the metal gate.

公开(公告)号：US20080135952A1

公开(公告)日：2008-06-12

申请号：US12031409

申请日：2008-02-14

Applicant: Justin K. Brask ,  Jack Kavalieros ,  Mark L. Doczy ,  Uday Shah ,  Chris E. Barns ,  Matthew V. Metz ,  Suman Datta ,  Annalisa Cappellani ,  Robert S. Chau

Inventor： Justin K. Brask ,  Jack Kavalieros ,  Mark L. Doczy ,  Uday Shah ,  Chris E. Barns ,  Matthew V. Metz ,  Suman Datta ,  Annalisa Cappellani ,  Robert S. Chau

IPC: H01L29/49

CPC classification number: H01L21/82345 ,  H01L21/28229 ,  H01L21/823842 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: A method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, then forming a trench within the first dielectric layer. After forming a second dielectric layer on the substrate, a first metal layer is formed within the trench on a first part of the second dielectric layer. A second metal layer is then formed on the first metal layer and on a second part of the second dielectric layer.

Abstract translation: 描述制造半导体器件的方法。 该方法包括在衬底上形成第一介电层，然后在第一介电层内形成沟槽。 在衬底上形成第二电介质层之后，在第二介电层的第一部分上的沟槽内形成第一金属层。 然后在第一金属层上和第二介电层的第二部分上形成第二金属层。

公开(公告)号：US07384880B2

公开(公告)日：2008-06-10

申请号：US10964464

申请日：2004-10-12

Applicant: Justin K. Brask ,  Jack Kavalieros ,  Mark L. Doczy ,  Matthew V. Metz ,  Suman Datta ,  Robert S. Chau

Inventor： Justin K. Brask ,  Jack Kavalieros ,  Mark L. Doczy ,  Matthew V. Metz ,  Suman Datta ,  Robert S. Chau

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L21/823462

Abstract: A method for making a semiconductor device is described. That method comprises converting a hydrophobic surface of a substrate into a hydrophilic surface, and forming a high-k gate dielectric layer on the hydrophilic surface.

Abstract translation: 描述制造半导体器件的方法。 该方法包括将基底的疏水表面转化为亲水表面，以及在亲水表面上形成高k栅介质层。

公开(公告)号：US20080087985A1

公开(公告)日：2008-04-17

申请号：US11998236

申请日：2007-11-29

Applicant: Justin Brask ,  Jack Kavalieros ,  Mark Doczy ,  Matthew Metz ,  Suman Datta ,  Uday Shah ,  Gilbert Dewey ,  Robert Chau

Inventor： Justin Brask ,  Jack Kavalieros ,  Mark Doczy ,  Matthew Metz ,  Suman Datta ,  Uday Shah ,  Gilbert Dewey ,  Robert Chau

IPC: H01L23/58

CPC classification number: H01L21/0228 ,  H01L21/02052 ,  H01L21/02175 ,  H01L21/28167 ,  H01L21/3141 ,  H01L29/513 ,  H01L29/517 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A buffer layer and a high-k metal oxide dielectric may be formed over a smooth silicon substrate. The substrate smoothness may reduce column growth of the high-k metal oxide gate dielectric. The surface of the substrate may be saturated with hydroxyl terminations prior to deposition.

Abstract translation: 可以在平滑的硅衬底上形成缓冲层和高k金属氧化物电介质。 衬底平滑度可能降低高k金属氧化物栅极电介质的柱生长。 在沉积之前，衬底的表面可能被羟基终止物饱和。

公开(公告)号：US07323423B2

公开(公告)日：2008-01-29

申请号：US10882734

申请日：2004-06-30

Applicant: Justin K. Brask ,  Jack Kavalieros ,  Mark L. Doczy ,  Matthew V. Metz ,  Suman Datta ,  Uday Shah ,  Gilbert Dewey ,  Robert S. Chau

Inventor： Justin K. Brask ,  Jack Kavalieros ,  Mark L. Doczy ,  Matthew V. Metz ,  Suman Datta ,  Uday Shah ,  Gilbert Dewey ,  Robert S. Chau

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L21/0228 ,  H01L21/02052 ,  H01L21/02175 ,  H01L21/28167 ,  H01L21/3141 ,  H01L29/513 ,  H01L29/517 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A buffer layer and a high-k metal oxide dielectric may be formed over a smooth silicon substrate. The substrate smoothness may reduce column growth of the high-k metal oxide gate dielectric. The surface of the substrate may be saturated with hydroxyl terminations prior to deposition.

Abstract translation: 可以在平滑的硅衬底上形成缓冲层和高k金属氧化物电介质。 衬底平滑度可能降低高k金属氧化物栅极电介质的柱生长。 在沉积之前，衬底的表面可能被羟基终止物饱和。

公开(公告)号：US20070264837A1

公开(公告)日：2007-11-15

申请号：US11382428

申请日：2006-05-09

Applicant: Willy Rachmady ,  James Blackwell ,  Suman Datta ,  Jack Kavalieros ,  Mantu Hudait

Inventor： Willy Rachmady ,  James Blackwell ,  Suman Datta ,  Jack Kavalieros ,  Mantu Hudait

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L21/31616 ,  H01L21/02178 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/28264 ,  H01L29/513 ,  H01L29/78

Abstract: Embodiments of the invention provide a method to form a high-k dielectric layer on a group III-V substrate with substantially no oxide of the group III-V substrate between the substrate and high-k dielectric layer. Oxide may be removed from the substrate. An organometallic compound may form a capping layer on the substrate from which the oxide was removed. The high-k dielectric layer may then be formed, resulting in a thin transition layer between the substrate and high-k dielectric layer and substantially no oxide of the group III-V substrate between the substrate and high-k dielectric layer.

Abstract translation: 本发明的实施例提供了在基板和高k电介质层之间基本上不具有III-V族衬底的氧化物的III-V族衬底上形成高k电介质层的方法。 氧化物可以从衬底去除。 有机金属化合物可以在去除氧化物的基底上形成覆盖层。 然后可以形成高k电介质层，导致衬底和高k电介质层之间的薄过渡层，并且在衬底和高k电介质层之间基本上不存在III-V族衬底的氧化物。

公开(公告)号：US20070235763A1

公开(公告)日：2007-10-11

申请号：US11393168

申请日：2006-03-29

Applicant: Brian Doyle ,  Been-Yih Jin ,  Jack Kavalieros ,  Suman Datta

Inventor： Brian Doyle ,  Been-Yih Jin ,  Jack Kavalieros ,  Suman Datta

IPC: H01L27/10 ,  H01L29/739

CPC classification number: H01L29/78687 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/78609

Abstract: A multi-gate transistor and a method of forming a multi-gate transistor, the multi-gate transistor including a fin having an upper portion and a lower portion. The upper portion having a first band gap and the lower portion having a second band gap with the first band gap and the second band gap designed to inhibit current flow from the upper portion to the lower portion. The multi-gate transistor further including a gate structure having sidewalls electrically coupled with said upper portion and said lower portion and a substrate positioned below the fin.

Abstract translation: 多栅极晶体管和形成多栅极晶体管的方法，所述多栅极晶体管包括具有上部和下部的鳍。 所述上部具有第一带隙，并且所述下部具有与所述第一带隙和所述第二带隙的第二带隙，所述第二带隙被设计成阻止电流从所述上部向下部流动。 多栅极晶体管还包括具有与所述上部和所述下部电耦合的侧壁的栅极结构和位于鳍下方的衬底。

公开(公告)号：US07279375B2

公开(公告)日：2007-10-09

申请号：US11173866

申请日：2005-06-30

Applicant: Marko Radosavljevic ,  Amlan Majumdar ,  Brian S. Doyle ,  Jack Kavalieros ,  Mark L. Doczy ,  Justin K. Brask ,  Uday Shah ,  Suman Datta ,  Robert S. Chau

Inventor： Marko Radosavljevic ,  Amlan Majumdar ,  Brian S. Doyle ,  Jack Kavalieros ,  Mark L. Doczy ,  Justin K. Brask ,  Uday Shah ,  Suman Datta ,  Robert S. Chau

IPC: H01L21/336

CPC classification number: H01L29/785 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78681 ,  H01L29/78684 ,  H01L2029/7858

Abstract: A contact architecture for nanoscale channel devices having contact structures coupling to and extending between source or drain regions of a device having a plurality of parallel semiconductor bodies. The contact structures being able to contact parallel semiconductor bodies having sub-lithographic pitch.