Abstract:
A method of manufacturing a semiconductor device may include forming a fin structure on an insulator and forming a gate structure over a channel portion of the fin structure. The method may also include forming a sacrificial oxide layer around the gate structure and removing the gate structure to define a gate recess within the sacrificial oxide layer. A metal gate may be formed in the gate recess, and the sacrificial oxide layer may be removed.
Abstract:
A semiconductor device, a semiconductor wafer and a method of forming a semiconductor wafer where a barrier layer is used to inhibit P-type ion-penetration into a dielectric layer made from a high-K material.
Abstract:
A double gate MOSFET. The MOSFET includes a bottom gate electrode and a bottom gate dielectric disposed over the bottom gate electrode. A semiconductor body region is disposed over the bottom gate dielectric and the bottom gate electrode, and disposed between a source and a drain. A top gate electrode is disposed over the body. A top gate dielectric separates the top gate electrode and the body, the top gate electrode and the bottom gate electrode defining a channel within the body and interposed between the source and the drain. At least one of the bottom gate dielectric or the top gate dielectric is formed from a high-K material. A method of forming a double gate MOSFET is also disclosed where a semiconductor film used to form a body is recrystallized using a semiconductor substrate as a seed crystal.
Abstract:
A method of fabricating an integrated circuit with a transistor having less susceptibility to off-state leakage current and short-channel effect is disclosed. The transistor includes high-K gate dielectric spacers and a T-shaped gate conductor. The high-K dielectric spacers can be tantalum pentaoxide or titanium dioxide. The process can be utilized for P-channel or N-channel metal oxide field semiconductor effect transistors (MOSFETs). The T-shaped conductor forms dynamic source/drain extensions.
Abstract:
A method for improving the channel doping profile of deep-submicron field effect transistors and MOSFETs. The method involves dual halo implants annealed at different temperatures to improve the threshold voltage roll-off characteristics of MOSFETs of approximately 50 nm or less. The method includes a deep source/drain implant and anneal, followed by an angled deep halo implant and a second anneal at a lower temperature. An amorphization implant is then made, followed by a second angled halo implant, formation of source/drain extensions and a third anneal at a temperature less than the second anneal.
Abstract:
A method of manufacturing an integrated circuit utilizes a thin film substrate and a high-k gate dielectric. The method includes providing a mask structure on a top surface of the thin film, depositing a semiconductor material above the top surface of the thin film and the mask structure, removing the semiconductor material to a level below the top surface of the mask structure, siliciding the semiconductor material, and providing a gate structure in an aperture formed by removing the mask structure. The transistor can be a fully depleted transistor having material for siliciding source and drain regions.
Abstract:
For fabricating a field effect transistor on a semiconductor substrate in SOI (semiconductor on insulator) technology, a pillar of semiconductor material is formed on a layer of buried insulating material. The pillar has a top surface and first and second side surfaces, and the pillar has a width, a length, and a height. A masking structure is formed on a center portion of the top surface of the pillar along the length of the pillar. A top portion of the height of the pillar is etched from exposed surfaces of the top surface of the pillar down to a bottom portion of the height of the pillar to form an upside down T-shape for the pillar. A gate dielectric material is deposited on any exposed surface of the semiconductor material of the pillar for a gate length along the length of the pillar. A gate electrode material is deposited on the gate dielectric material to surround the pillar for the gate length of the pillar. A drain and source dopant is implanted into exposed regions of the pillar to form a drain of the field effect transistor on a first side of the gate electrode material along the length of the pillar and to form a source of the field effect transistor on a second side of the gate electrode material along the length of the pillar. In this manner, for a given height and width of the semiconductor pillar, any point of a cross-section of such a pillar is more closely located to the gate bias applied at a surface of such a pillar to maximize effective drive current while minimizing undesired short channel effects of the field effect transistor.
Abstract:
The invention provides an improved well structure for electrically separating n-channel and p-channel MOSFETs. The invention first forms a shallow well in a substrate. A buried amorphous layer is then formed below the shallow well. A deep well is then formed below the buried amorphous layer. The substrate is then subjected to a rapid thermal anneal to recrystallize the buried amorphous layer. The well structure is formed by the shallow well and the deep well. A conventional semiconductor device may then be formed above the well structure. The buried amorphous layer suppresses the channeling effect during the forming of the deep well without requiring a tilt angle.
Abstract:
A transistor device formed on a semiconductor-on-insulator (SOI) substrate with a buried oxide (BOX) layer disposed thereon and an active layer disposed on the BOX layer having active regions defined by isolation trenches. The device includes a gate defining a channel interposed between a source and a drain formed within the active region of the SOI substrate. Further, the device includes a multi-thickness silicide layer formed on the main source and drain regions and source and drain extension regions wherein a portion of the multi-thickness silicide layer which is formed on the source and drain extension regions is thinner than a portion of the silicide layer which is formed on the main source and drain regions. The device further includes a second thin silicide layer formed on a polysilicon electrode of the gate.
Abstract:
The disclosure includes an exemplary embodiment which relates to a method of forming L-shaped spacers in an integrated circuit. This method can include providing a gate structure over a semiconductor substrate, depositing a spacer material adjacent lateral sides of the gate structure, forming dummy oxide spacer structures over the spacer material where the dummy oxide spacer structures are shaped to selectively cover an L-shaped portion of the spacer material, removing portions of the spacer material not covered by the dummy oxide spacer structures, and removing the dummy oxide spacer structures.