公开(公告)号：US20050286380A1

公开(公告)日：2005-12-29

申请号：US10876030

申请日：2004-06-24

Applicant: Chang Kang

Inventor： Chang Kang

IPC: G11B5/09 ,  H03H17/02

CPC classification number: H03H17/0219

Abstract: An adaptive digital hysteresis technique where two modes are used to develop the output value, rather than the conventional single rounding technique, to reduce the quantization errors. To determine which of two different schemes, referred to as floor and ceil, to use, there are trip points to select modes. The floor and ceiling trip points are developed based on the value of the input signal. When the trip point for the other mode is exceeded and the next trip point for the current mode is not exceeded, the mode is changed. The output values of the technique have a lower error than the prior art rounding with hysteresis techniques.

Abstract translation: 一种自适应数字滞后技术，其中使用两种模式来产生输出值，而不是传统的单舍入技术来减少量化误差。 要确定两种不同的方案（称为floor和ceil）中哪一种使用，有选择模式的跳闸点。 基于输入信号的值开发地板和天花板跳点。 超过其他模式的跳闸点时，不超过当前模式的下一个跳闸点，则更改模式。 该技术的输出值比现有技术使用滞后技术的舍入误差更小。

公开(公告)号：US06973152B2

公开(公告)日：2005-12-06

申请号：US10310554

申请日：2002-12-04

Applicant: Kevin Paul Gross

Inventor： Kevin Paul Gross

IPC: H04L29/08 ,  H03D3/24

CPC classification number: H04L69/323

Abstract: Apparatus and methods are provided for exploiting the existence of a shortest path between a source device and a destination device by identifying the shortest path and using the signal which has taken the shortest path in preference to delayed transmissions or delayed images of the same signal, thereby improving signal distribution. The present invention provides a processor between a phase-sensitive detector and a low pass filter of a phase locked loop for selecting and driving the PLL primarily from the signal which has taken the shortest path.

Abstract translation: 提供装置和方法，用于通过识别最短路径并使用优先采用最短路径的信号优先于相同信号的延迟传输或延迟图像，从而在源设备和目的地设备之间存在最短路径，由此 改善信号分布。 本发明提供了相位敏感检测器和锁相环路的低通滤波器之间的处理器，用于主要从采取最短路径的信号中选择和驱动PLL。

公开(公告)号：US06965335B1

公开(公告)日：2005-11-15

申请号：US10765443

申请日：2004-01-27

Applicant: Brian David Trotter ,  Bruce Duewer ,  John Laurence Melanson

Inventor： Brian David Trotter ,  Bruce Duewer ,  John Laurence Melanson

IPC: H03M1/66 ,  H03M3/00 ,  H03M7/36

CPC classification number: H03M7/3006 ,  H02M2003/1586 ,  H03M3/506 ,  H03M7/3015 ,  H03M7/3026 ,  H03M7/3037

Abstract: A method of performing digital to analog conversion includes generating a pulse width modulated data stream and another pulse width modulated data stream, encoding patterns of the pulse width modulated data stream selected to minimize distortion in the another pulse width modulated stream caused by edges in the pulse width modulated data stream. The pulse width modulated data stream and the another pulse width modulated data stream are converted into an analog signal and another analog signal converting in corresponding digital to analog conversion elements and the analog signal and the another analog signal are summed to generate an analog output signal.

Abstract translation: 执行数模转换的方法包括生成脉冲宽度调制数据流和另一个脉宽调制数据流，编码脉宽调制数据流的模式，以选择最小化由脉冲中的边缘引起的另一个脉宽调制流中的失真 宽度调制数据流。 将脉冲宽度调制数据流和另一个脉冲宽度调制数据流转换成模拟信号，并在相应的数/模转换元件中转换另一个模拟信号，并将模拟信号和另一模拟信号相加以产生模拟输出信号。

公开(公告)号：US06948098B2

公开(公告)日：2005-09-20

申请号：US09822052

申请日：2001-03-30

Applicant: Sanjay Ramakrishna Pillay ,  Raghunath Krishna Rao

Inventor： Sanjay Ramakrishna Pillay ,  Raghunath Krishna Rao

IPC: G01R31/317 ,  G06F11/267 ,  G06F11/00

CPC classification number: G06F11/2236 ,  G01R31/31701 ,  G01R31/31704 ,  G01R31/31705

Abstract: A debugging subsystem for testing a system-on-a-chip includes an embedded processor and memory and includes at least one debugging subblock monitors a bus between the processor and the memory to detect selected triggering events, counts the number of triggering events detected and when the number of triggering events reaches a predetermined threshold, generates a debugging signal.

Abstract translation: 用于测试片上系统的调试子系统包括嵌入式处理器和存储器，并且包括至少一个调试子块监视处理器和存储器之间的总线以检测所选择的触发事件，计数检测到的触发事件的数量和何时 触发事件的数量达到预定的阈值，产生调试信号。

公开(公告)号：US06937046B1

公开(公告)日：2005-08-30

申请号：US10027187

申请日：2001-12-20

Applicant: Murari Kejariwal ,  Prasad Ammisetti ,  Axel Thomsen ,  John Laurence Melanson

Inventor： Murari Kejariwal ,  Prasad Ammisetti ,  Axel Thomsen ,  John Laurence Melanson

IPC: G01R31/28 ,  G01R31/02

CPC classification number: G01R31/2884

Abstract: A method of testing an integrated circuit including the steps of observing a selected parameter at a selected test mode to detect an error. The current to the integrated circuit is stepped from a reference level by selected amount.

Abstract translation: 一种测试集成电路的方法，包括在所选择的测试模式下观察所选择的参数以检测错误的步骤。 到集成电路的电流从参考电平以选定的量步进。

公开(公告)号：US06885211B1

公开(公告)日：2005-04-26

申请号：US10117374

申请日：2002-04-05

Applicant: Axel Thomsen ,  Sherry Wu ,  Murari Kejariwal ,  Ammisetti Prasad ,  John Laurence Melanson

Inventor： Axel Thomsen ,  Sherry Wu ,  Murari Kejariwal ,  Ammisetti Prasad ,  John Laurence Melanson

IPC: G01R31/28 ,  G01R31/26

CPC classification number: G01R31/2837

Abstract: A method of testing an integrated circuit includes setting a guardbanded limit for a parameter associated with an embedded node, a deviation from the guardbanded limit under a set of test conditions correlated with a failure of the integrated circuit across a range of operating conditions. A test is performed under the test conditions to detect deviations of the parameter from the guardbanded limit to detect failures of the integrated circuit over the range of operating conditions.

Abstract translation: 一种测试集成电路的方法包括设置与嵌入式节点相关联的参数的保护限值，与在整个操作条件范围内的集成电路的故障相关的一组测试条件下的保护带限制的偏差。 在测试条件下进行测试，以检测参数与防护带限制的偏差，以检测集成电路在工作条件范围内的故障。

公开(公告)号：US20050052304A1

公开(公告)日：2005-03-10

申请号：US10656749

申请日：2003-09-05

Applicant: Brian Trotter ,  Bruce Duewer ,  John Melanson

Inventor： Brian Trotter ,  Bruce Duewer ,  John Melanson

IPC: H03M1/06 ,  H03M1/08 ,  H03M1/66 ,  H03M3/04 ,  H03M1/82

CPC classification number: H03M3/506

Abstract: A pulse width modulator includes at least one input for receiving an input signal and pulse width modulation circuitry for generating a pulse width modulated stream and another pulse width modulated stream. The pulse width modulated stream and the another pulse width modulated stream are nominally out of phase and together represent the received input signal. A summer sums the pulse width modulated stream and the another pulse width modulated stream to generate an analog output signal.

Abstract translation: 脉冲宽度调制器包括用于接收输入信号的至少一个输入端和用于产生脉冲宽度调制流和另一脉冲宽度调制流的脉宽调制电路。 脉冲宽度调制流和另一脉冲宽度调制流标称上是异相的，并且一起表示所接收的输入信号。 夏季将脉冲宽度调制流和另一脉冲宽度调制流相加以产生模拟输出信号。

公开(公告)号：US20050010399A1

公开(公告)日：2005-01-13

申请号：US10463947

申请日：2003-06-17

Applicant: Bruce Duewer

Inventor： Bruce Duewer

IPC: G06F1/22 ,  G10L19/00

CPC classification number: G11B20/10527 ,  G06F1/22 ,  G11B2020/00065 ,  G11B2020/10583

Abstract: A method of controlling a terminal of an integrated circuit includes determining a frequency ratio between a frequency of a signal and a frequency of another signal received by an integrated circuit. A selected signal appearing at a selected terminal of the integrated circuit is selectively interpreted in accordance with an operating mode when the frequency ratio is below a selected value and in accordance with another operating mode when the frequency of the signal is above a selected value.

Abstract translation: 控制集成电路的端子的方法包括确定信号的频率与由集成电路接收的另一信号的频率之间的频率比。 当频率低于所选值时，并且当信号的频率高于选定值时，根据另一操作模式，选择性地根据工作模式来解释出现在集成电路的选定端的选择信号。

公开(公告)号：US20040210801A1

公开(公告)日：2004-10-21

申请号：US10417443

申请日：2003-04-16

Applicant: Cirrus Logic, Inc.

Inventor： Ammisetti V. Prasad ,  Karl Thompson ,  John Laurence Melanson ,  Shyam Somayajula

IPC: G11B005/00 ,  G06K005/04 ,  G11B020/20

CPC classification number: G11C27/024

Abstract: A sample and hold circuit including a sampling capacitor for storing a sample of an input signal, an output stage for outputting the sample stored on the sampling capacitor; and input circuitry for sampling the input signal and storing the sample on the sampling capacitor. The input circuitry includes an autozeroing input buffer which selectively samples the input signal during a first operating phase and holds a sample of the input signal during a second operating phase. The autozeroing input buffer cancels any offset error. The input circuitry also includes switching circuitry for selectively coupling the sampling capacitor with an input of the sample and hold circuitry during the second operating phase and to an output of the autozeroing input buffer during the first operating phase.

Abstract translation: 一种采样保持电路，包括用于存储输入信号的采样的采样电容器，用于输出存储在采样电容器上的样本的输出级; 以及用于对输入信号进行采样并将采样存储在采样电容器上的输入电路。 输入电路包括自动调零输入缓冲器，其在第一操作阶段期间选​​择性地采样输入信号，并且在第二操作阶段期间保持输入信号的采样。 自动归零输入缓冲器取消任何偏移误差。 输入电路还包括用于在第二操作阶段期间将采样电容器与采样和保持电路的输入有选择地耦合的开关电路，以及在第一操作阶段期间自动调零输入缓冲器的输出。

公开(公告)号：US20040135608A1

公开(公告)日：2004-07-15

申请号：US10200824

申请日：2002-07-22

Applicant: Cirrus Logic, Inc.

Inventor： Sanjay Pillay ,  Khoi Mai ,  Luo Zheng ,  Dimitri Pantelakis

IPC: H03K003/017

CPC classification number: H03K5/1565

Abstract: A signal generator generates an output signal with a programmable duty cycle and includes a first buffer which generates in response to an input signal an intermediate signal having a selected edge with a voltage slope selected to vary a length of a selected phase of the output signal. A second buffer having a selected input voltage threshold generates the output signal in response to the intermediate signal.

Abstract translation: 信号发生器产生具有可编程占空比的输出信号，并且包括第一缓冲器，其响应于输入信号产生具有选择的边沿的中间信号，所述边沿具有选择的电压斜率以改变输出信号的选定相位的长度。 具有选择的输入电压阈值的第二缓冲器响应于中间信号产生输出信号。