公开(公告)号：USD562398S1

公开(公告)日：2008-02-19

申请号：US29266896

申请日：2006-09-27

Applicant: Zhiming Qiu ,  Bin Li

Designer： Zhiming Qiu ,  Bin Li

公开(公告)号：US07286363B2

公开(公告)日：2007-10-23

申请号：US11168068

申请日：2005-06-28

Applicant: Hsieh-Kun Lee ,  Wan-Lin Xia ,  Bao-Chun Chen ,  Neng-Bin Li

Inventor： Hsieh-Kun Lee ,  Wan-Lin Xia ,  Bao-Chun Chen ,  Neng-Bin Li

IPC: H05K7/20 ,  F28F7/00

CPC classification number: H01L23/4093 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A heat dissipation assembly includes a heat sink, a retention module and a clip for securing the heat sink to the retention module. The heat sink includes a base for contacting with a heat generating device. The retention module includes a bottom wall and a first sidewall defining a slot therein and extending from the bottom wall. The clip includes a connecting portion pivotably connected to the retention module. The heat sink rests on the bottom wall of the retention module with an end thereof fitting in the slot, and an opposite end thereof being pressed by the clip. The clip can be in a released position that the clip is pivotable, so that the heat sink is removable from the retention module, and a locked position that the clip presses the heat sink. Thus, the heat sink can be secured to the heat generating device expediently.

Abstract translation: 散热组件包括散热器，保持模块和用于将散热器固定到保持模块的夹子。 散热器包括用于与发热装置接触的基座。 保持模块包括底壁和在其中限定槽并从底壁延伸的第一侧壁。 夹具包括可枢转地连接到保持模块的连接部分。 散热片搁置在保持模块的底壁上，其一端装配在槽中，其相对端由夹子按压。 夹子可以处于释放位置，夹子可枢转，使得散热器可从保持模块移除，以及夹子按压散热器的锁定位置。 因此，散热器可以方便地固定到发热装置。

公开(公告)号：US20070126943A1

公开(公告)日：2007-06-07

申请号：US11295422

申请日：2005-12-05

Applicant: Mu-Chia Lee ,  Chun-Wei Huang ,  Hung-Che Lu ,  Kuo-Hung Kuo ,  Hong-Bin Li ,  Wen-Kuei Lai ,  Chia-Yi Tsai ,  Yu-Chi Chang ,  Hau-Chiun Li ,  Wei-Chih Chang

Inventor： Mu-Chia Lee ,  Chun-Wei Huang ,  Hung-Che Lu ,  Kuo-Hung Kuo ,  Hong-Bin Li ,  Wen-Kuei Lai ,  Chia-Yi Tsai ,  Yu-Chi Chang ,  Hau-Chiun Li ,  Wei-Chih Chang

IPC: G02F1/1343

CPC classification number: G02F1/136213 ,  G02F2201/18

Abstract: The invention discloses a stacked storage capacitor structure for a LTPS TFT-LCD comprising a processed substrate, a first storage capacitor and a second storage capacitor. The first storage capacitor comprises a first conductive layer, a second conductive layer and a first insulating layer therebetween. The stacked storage capacitor structure further comprises a third conductive layer including a first portion and an extended second portion. The second storage capacitor comprises the second conductive layer, the extended second portion of the third conductive layer and a second insulating layer therebetween.

Abstract translation: 本发明公开了一种包括处理衬底，第一存储电容器和第二存储电容器的LTPS TFT-LCD的堆叠存储电容器结构。 第一存储电容器包括第一导电层，第二导电层和第一绝缘层。 层叠的存储电容器结构还包括第三导电层，其包括第一部分和延伸的第二部分。 第二存储电容器包括第二导电层，第三导电层的延伸的第二部分和其间的第二绝缘层。

公开(公告)号：US07215646B2

公开(公告)日：2007-05-08

申请号：US10940079

申请日：2004-09-14

Applicant: Philip J. Pietraski ,  Gregory S. Sternberg ,  Rui Yang ,  Bin Li

Inventor： Philip J. Pietraski ,  Gregory S. Sternberg ,  Rui Yang ,  Bin Li

IPC: G01R31/08 ,  G06F11/00 ,  H04J1/16 ,  H04L12/26 ,  H04L27/06 ,  H03D1/00 ,  H03D1/04

CPC classification number: H04L1/0026 ,  H04L1/20 ,  H04L25/0202

Abstract: A method and apparatus for estimating and reporting the quality of a wireless communication channel between a wireless transmit/receive unit (WTRU) and a Node-B. A modulated signal is received from the Node-B over the communication channel and a channel estimation is performed on the modulated signal to provide a channel estimate. In one embodiment, the modulated signal is demodulated based on the channel estimate to provide a demodulated signal and a signal-to-interference (SIR) estimate based on the demodulated signal is obtained. The quality of the communication channel is estimated based on at least the SIR estimate. In an alternate embodiment, a SIR estimate based on the channel estimate is obtained. The quality of the communication channel is estimated based on the SIR estimate and additional information including at least one of delay spread, transmit power and WTRU velocity information.

Abstract translation: 一种用于估计和报告无线发射/接收单元（WTRU）和节点B之间的无线通信信道的质量的方法和装置。 通过通信信道从节点B接收调制信号，并对调制信号执行信道估计以提供信道估计。 在一个实施例中，基于信道估计来解调调制信号以提供解调信号，并且获得基于解调信号的信号干扰（SIR）估计。 至少基于SIR估计来估计通信信道的质量。 在替代实施例中，获得基于信道估计的SIR估计。 基于SIR估计和包括延迟扩展，发射功率和WTRU速度信息中的至少一个的附加信息来估计通信信道的质量。

公开(公告)号：US07173978B2

公开(公告)日：2007-02-06

申请号：US09912068

申请日：2001-07-23

Applicant: Song Zhang ,  Bin Li ,  Andrew Deczky ,  Alberto Ginesi

Inventor： Song Zhang ,  Bin Li ,  Andrew Deczky ,  Alberto Ginesi

IPC: H04L27/36

CPC classification number: H04L1/006 ,  H04L1/0041 ,  H04L1/0057 ,  H04L1/0066 ,  H04L1/0068 ,  H04L1/0069 ,  H04L5/023 ,  H04L27/2602

Abstract: In a coding system for asymmetric digital subscriber line (ADSL) communications, a method of encoding a sequence of information bits is provided comprising the steps of dividing the information bits into encoding bits and parallel bits; encoding the encoding bits to produce encoded bits; mapping the encoded bits and the parallel bits into first and second pulse amplitude modulation (PAM) signals; and generating a quadrature amplitude modulation (QAM) signal from these first and second PAM signals. This method overcomes the decoder complexity that would otherwise be required due to the large QAM constellations involved for ADSL communications.

Abstract translation: 在用于非对称数字用户线（ADSL）通信的编码系统中，提供一种编码信息比特序列的方法，包括以下步骤：将信息比特划分为编码比特和并行比特; 对编码比特进行编码以产生编码比特; 将编码比特和并行比特映射到第一和第二脉冲幅度调制（PAM）信号中; 以及从这些第一和第二PAM信号产生正交幅度调制（QAM）信号。 该方法克服了由于ADSL通信涉及的大的QAM星座而将需要的解码器复杂度。

公开(公告)号：US07106780B2

公开(公告)日：2006-09-12

申请号：US10725788

申请日：2003-12-02

Applicant: Bin Li ,  Alexander Reznik

Inventor： Bin Li ,  Alexander Reznik

IPC: H04B15/00 ,  H04K1/00 ,  H04L27/30

CPC classification number: H04B1/712 ,  H04B7/0854

Abstract: A receiver comprises a plurality of antenna elements for receiving a data signal. Each antenna element has a plurality of Rake fingers. Each Rake finger processes a received multipath component of the received data signal of its antenna element by applying a complex weight gain to that received multipath component. A complex weight gain generator determines the complex weight gain for each Rake finger for each antenna element using an input from all the Rake fingers. A summer combines an output of each Rake finger to produce an estimate of the data signal.

Abstract translation: 接收机包括用于接收数据信号的多个天线元件。 每个天线元件具有多个耙指。 每个Rake指针通过对所接收的多路径分量应用复加权增益来处理其天线元件的接收数据信号的接收多径分量。 复合加权增益发生器使用来自所有耙指的输入来确定每个天线元件的每个耙指的复重加权增益。 夏季结合了每个Rake指针的输出以产生数据信号的估计。

公开(公告)号：US07099187B2

公开(公告)日：2006-08-29

申请号：US11225953

申请日：2005-09-14

Applicant: Bin Li ,  Kenneth R. Knowles ,  David C. Lawson

Inventor： Bin Li ,  Kenneth R. Knowles ,  David C. Lawson

IPC: G11C11/00

CPC classification number: G11C13/0004 ,  G11C13/0038 ,  G11C13/004

Abstract: A read/write circuit for accessing chalcogenide non-volatile memory cells is disclosed. The read/write circuit includes a chalcogenide storage element, a voltage limiting circuit, a current-to-voltage converter, and a buffer circuit. The voltage limiting circuit, which is coupled to the chalcogenide storage element, ensures that voltages across the chalcogenide storage element will not exceed a predetermined value during a read operation. During a read operation, the current-to-voltage converter, which is coupled to the voltage limiting circuit, converts a current pulse read from the chalcogenide storage element to a voltage pulse. By sensing the voltage pulse from the current-to-voltage converter, the buffer circuit can determine a storage state of the chalcogenide storage element.

公开(公告)号：US06996160B2

公开(公告)日：2006-02-07

申请号：US10718394

申请日：2003-11-20

Applicant: Bin Li ,  Alexander Reznik

Inventor： Bin Li ,  Alexander Reznik

IPC: H04B1/69

CPC classification number: H04L25/0232 ,  H04B1/712 ,  H04B2201/70701

Abstract: A channel estimation method which reduces the strain on resources of a Rake receiver using a complex weight gain (CWG) algorithm. In one embodiment, a non-adaptive algorithm is used to average blocks of pilot symbols from several slots. In another embodiment, an adaptive algorithm implements sliding window averaging or a recursive filter. Using a CWG algorithm reduces the memory and processor requirements of the Rake receiver.

Abstract translation: 一种信道估计方法，其使用复加权增益（CWG）算法来减少Rake接收机的资源的应变。 在一个实施例中，使用非自适应算法来平均几个时隙中的导频符号块。 在另一个实施例中，自适应算法实现滑动窗口平均或递归滤波器。 使用CWG算法可以降低Rake接收机的内存和处理器要求。

公开(公告)号：US20060013037A1

公开(公告)日：2006-01-19

申请号：US11225953

申请日：2005-09-14

Applicant: Bin Li ,  Kenneth Knowles ,  David Lawson

Inventor： Bin Li ,  Kenneth Knowles ,  David Lawson

IPC: G11C11/00

CPC classification number: G11C13/0004 ,  G11C13/0038 ,  G11C13/004

Abstract: A read/write circuit for accessing chalcogenide non-volatile memory cells is disclosed. The read/write circuit includes a chalcogenide storage element, a voltage limiting circuit, a current-to-voltage converter, and a buffer circuit. The voltage limiting circuit, which is coupled to the chalcogenide storage element, ensures that voltages across the chalcogenide storage element will not exceed a predetermined value during a read operation. During a read operation, the current-to-voltage converter, which is coupled to the voltage limiting circuit, converts a current pulse read from the chalcogenide storage element to a voltage pulse. By sensing the voltage pulse from the current-to-voltage converter, the buffer circuit can determine a storage state of the chalcogenide storage element.

Abstract translation: 公开了用于访问硫族化物非易失性存储器单元的读/写电路。 读/写电路包括硫族化物存储元件，电压限制电路，电流 - 电压转换器和缓冲电路。 耦合到硫族化物存储元件的电压限制电路确保在读取操作期间跨越硫族化物存储元件的电压不会超过预定值。 在读取操作期间，耦合到电压限制电路的电流 - 电压转换器将从硫族化物存储元件读取的电流脉冲转换为电压脉冲。 通过感测来自电流 - 电压转换器的电压脉冲，缓冲电路可以确定硫族化物存储元件的存储状态。

公开(公告)号：US06965521B2

公开(公告)日：2005-11-15

申请号：US10631174

申请日：2003-07-31

Applicant: Bin Li ,  Kenneth R. Knowles ,  David C. Lawson

Inventor： Bin Li ,  Kenneth R. Knowles ,  David C. Lawson

IPC: G11C11/00 ,  G11C16/02 ,  G11C16/26

CPC classification number: G11C13/0004 ,  G11C13/0038 ,  G11C13/004

Abstract: A read/write circuit for accessing chalcogenide non-volatile memory cells is disclosed. The read/write circuit includes a chalcogenide storage element, a voltage limiting circuit, a current-to-voltage converter, and a buffer circuit. The voltage limiting circuit, which is coupled to the chalcogenide storage element, ensures that voltages across the chalcogenide storage element will not exceed a predetermined value during a read operation. During a read operation, the current-to-voltage converter, which is coupled to the voltage limiting circuit, converts a current pulse read from the chalcogenide storage element to a voltage pulse. By sensing the voltage pulse from the current-to-voltage converter, the buffer circuit can determine a storage state of the chalcogenide storage element.