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    Method evaluating threshold level of a data cell in a memory device
    251.
    发明授权
    Method evaluating threshold level of a data cell in a memory device 有权
    方法评估存储器件中数据单元的阈值水平

    公开(公告)号：US07516037B2

    公开(公告)日：2009-04-07

    申请号：US11755891

    申请日：2007-05-31

    Applicant: David John Baldwin ,  Eric Blackall ,  Joseph Devore ,  Ross E. Teggatz

    Inventor： David John Baldwin ,  Eric Blackall ,  Joseph Devore ,  Ross E. Teggatz

    IPC: G06F15/00

    CPC classification number: G11C16/34

    Abstract: A method evaluating threshold of a data cell in a memory device including a programming locus coupled with the data cell for receiving a programming signal setting a stored signal level in the data cell and responding to a read signal to indicate the stored signal at a read locus; includes the steps of: (a) in no particular order; (1) selecting a test threshold signal; and (2) setting a read signal at a non-read level; (b) applying the test threshold signal to the programming locus; (c) cycling the read signal between a read level and a non-read level while applying the test threshold signal to the programming locus to present at least two test signals at the read locus when the read signal is at the read level; and (d) while cycling, observing whether the at least two test signals manifest a difference greater than a predetermined amount.

    Abstract translation: 一种评估存储器件中的数据单元的阈值的方法，包括与所述数据单元耦合的编程轨迹，用于接收在所述数据单元中设置存储的信号电平的编程信号，并且响应于读取信号以指示所读取的位置处存储的信号 ; 包括以下步骤：（a）没有特别的顺序; （1）选择测试阈值信号; 和（2）以非读取级别设置读取信号; （b）将测试阈值信号应用于编程轨迹; （c）在读取电平和非读取电平之间循环读取信号，同时当读取信号处于读取电平时，将测试阈值信号施加到编程轨迹，以在读取轨迹处呈现至少两个测试信号; 和（d）循环时，观察至少两个测试信号是否表现出大于预定量的差。

    Method to control uniformity/composition of metal electrodes, silicides on topography and devices using this method
    252.
    发明申请
    Method to control uniformity/composition of metal electrodes, silicides on topography and devices using this method 有权
    控制金属电极的均匀性/组成的方法，使用这种方法的地形和器件上的硅化物

    公开(公告)号：US20080280429A1

    公开(公告)日：2008-11-13

    申请号：US11803097

    申请日：2007-05-11

    Applicant: Leo Mathew ,  Ross E. Noble ,  Raghaw S. Rai

    Inventor： Leo Mathew ,  Ross E. Noble ,  Raghaw S. Rai

    IPC: H01L21/3205

    CPC classification number: H01L21/32139 ,  H01L21/823828 ,  H01L29/66795 ,  H01L29/785

    Abstract: A method for depositing metals on surfaces is provided which comprises (a) providing a substrate (103) having a horizontal surface (107) and a vertical surface (105); (b) depositing a first metal layer (109) over the horizontal and vertical surfaces; (c) depositing a layer of polysilicon (111) over the horizontal and vertical surfaces; (d) treating the layer of polysilicon with a plasma such that a residue (113) remaining from the treatment is preferentially formed over the horizontal surfaces rather than the vertical surfaces, and wherein the residue is resistant to a first metal etch; and (e) exposing the substrate to the first metal etch.

    Abstract translation: 提供一种在表面上沉积金属的方法，其包括（a）提供具有水平表面（107）和垂直表面（105）的基底（103）; （b）在水平和垂直表面上沉积第一金属层（109）; （c）在水平和垂直表面上沉积多晶硅层（111）; （d）用等离子体处理多晶硅层，使得从处理中残留的残余物（113）优先形成在水平表面而不是垂直表面上，并且其中残余物耐第一金属蚀刻; 和（e）将衬底暴露于第一金属蚀刻。

    Selective barrier metal polishing method
    253.
    发明申请
    Selective barrier metal polishing method 有权
    选择性屏障金属抛光方法

    公开(公告)号：US20080119052A1

    公开(公告)日：2008-05-22

    申请号：US11975804

    申请日：2007-10-22

    Applicant: Zhendong Liu ,  Ross E. Barker

    Inventor： Zhendong Liu ,  Ross E. Barker

    IPC: H01L21/302

    CPC classification number: C09G1/02 ,  C09K3/1409 ,  C09K3/1463 ,  C23F3/06 ,  H01L21/3212 ,  H01L21/7684

    Abstract: The polishing method uses a polishing solution for removing barrier materials in the presence of interconnect metals and dielectrics. The polishing solution comprises, by weight percent, 0.1 to 10 hydrogen peroxide, at least one pH adjusting agent selected from the group consisting of nitric acid, sulfuric acid, hydrochloric acid and phosphoric acid for adjusting a pH level of the polishing solution to less than 3, at least 0.0025 benzotriazole inhibitor for reducing removal rate of the interconnect metals, 0 to 10 surfactant, 0.01 to 10 colloidal silica having an average particle size of less than 50 nm and balance water and incidental impurities. The polishing solution has a tantalum nitride material to copper selectivity of at least 3 to 1 and a tantalum nitride to TEOS selectivity of at least 3 to 1.

    Abstract translation: 抛光方法使用在互连金属和电介质存在下去除阻挡材料的抛光溶液。 抛光溶液以重量百分比计包含0.1至10种过氧化氢，至少一种选自硝酸，硫酸，盐酸和磷酸的pH调节剂，用于将抛光溶液的pH值调节至小于 3，至少含有0.0025的苯并三唑抑制剂，用于降低互连金属的去除速率，0至10表面活性剂，0.01至10个平均粒度小于50nm的胶体二氧化硅，余量为水和附带杂质。 抛光溶液的氮化钽材料至铜选择性为至少3比1，氮化钽至TEOS选择性为至少3比1。

    Cable side-entry sub with grease injection flow tubes
    254.
    发明授权
    Cable side-entry sub with grease injection flow tubes 有权
    电缆侧入口带油脂注射流管

    公开(公告)号：US07261155B1

    公开(公告)日：2007-08-28

    申请号：US10923973

    申请日：2004-08-23

    Applicant: Richard M. Ward ,  Ross E. Stevenson

    Inventor： Richard M. Ward ,  Ross E. Stevenson

    IPC: E21B17/02 ,  E21B41/00

    CPC classification number: E21B17/025

    Abstract: An integrated side-entry sub with grease injection flow tubes is adapted for making up in a drill string and includes a port to receive a cable, such as a wire line. A first pedestal, mounted within a cutout of the side entry sub, provides entry for the cable into the entry port. The first pedestal receives a first flow tube, which couples to a lower connector manifold. The lower connector manifold further provides a grease injection port. A second flow tube, coupled to the lower connector manifold, runs to an upper connector manifold. The upper connector manifold further provides an grease return port, as well an the entry point for cable into the sub.

    Abstract translation: 具有润滑脂注入流量管的集成侧入式底座适于组成钻柱，并且包括用于接收电缆（例如电线）的端口。 安装在侧入口子的切口内的第一基座提供电缆进入入口的入口。 第一基座接收第一流管，其连接到下连接器歧管。 下连接器歧管还提供润滑脂注入口。 耦合到下连接器歧管的第二流管延伸到上连接器歧管。 上连接器歧管还提供润滑脂返回口，以及电缆进入子进口的入口点。

    Programmable voltage regulator configurable for double power density and reverse blocking
    256.
    发明授权
    Programmable voltage regulator configurable for double power density and reverse blocking 有权
    可编程稳压器可配置双功率密度和反向阻塞

    公开(公告)号：US07071664B1

    公开(公告)日：2006-07-04

    申请号：US11017177

    申请日：2004-12-20

    Applicant: Ross E. Teggatz ,  Sanmukh M. Patel ,  Rex M. Teggatz ,  Suribhotla V. Rajasekhar ,  Valerian Mayega

    Inventor： Ross E. Teggatz ,  Sanmukh M. Patel ,  Rex M. Teggatz ,  Suribhotla V. Rajasekhar ,  Valerian Mayega

    IPC: G05F1/44

    CPC classification number: H02J7/0063

    Abstract: A programmable voltage regulator configurable for reverse blocking and double power density is disclosed herein. The programmable voltage regulator includes an error amplifier that couples to receive a reference voltage. A first NMOS pass transistor connects between an auxiliary voltage input node and the output terminal of the voltage regulator, wherein the first NMOS pass transistor is biased by the output of the error amplifier. Connected between the source of the first NMOS pass transistor and the second input of the error amplifier, a feedback network provides feedback for the voltage regulator. A second NMOS pass transistor connects between the first power supply and the auxiliary voltage input node. Furthermore, an independent node control circuit biases the second NMOS pass transistor such that in a first mode of operation, a first control signal input is operable to receive a signal for controlling the second NMOS pass transistor during reverse battery condition. In a second mode of operation, independent node control circuit includes a second control signal input that is operable to couple to the output terminal of the error amplifier while simultaneously the first power supply rail is operable to couple to the output terminal of the voltage regulator to provide double power density.

    Abstract translation: 本文公开了可配置用于反向阻塞和双功率密度的可编程电压调节器。 可编程电压调节器包括耦合以接收参考电压的误差放大器。 第一NMOS传输晶体管连接在辅助电压输入节点和电压调节器的输出端之间，其中第一NMOS传输晶体管被误差放大器的输出偏置。 连接在第一NMOS传输晶体管的源极和误差放大器的第二输入端之间，反馈网络为电压调节器提供反馈。 第二NMOS传输晶体管连接在第一电源和辅助电压输入节点之间。 此外，独立节点控制电路偏置第二NMOS传输晶体管，使得在第一操作模式中，第一控制信号输入可操作以在反向电池状态期间接收用于控制第二NMOS传输晶体管的信号。 在第二操作模式中，独立节点控制电路包括第二控制信号输入，其可操作以耦合到误差放大器的输出端，同时第一电源轨可操作以耦合到电压调节器的输出端， 提供双倍功率密度。

    Eucalyptus biomechanical pulping process
    258.
    发明授权
    Eucalyptus biomechanical pulping process 失效
    桉树生物力学制浆工艺

    公开(公告)号：US07008505B2

    公开(公告)日：2006-03-07

    申请号：US10478941

    申请日：2002-05-30

    Applicant: Masood Akhtar ,  Eric G. Horn ,  Michael J. Lentz ,  Ross E. Swaney

    Inventor： Masood Akhtar ,  Eric G. Horn ,  Michael J. Lentz ,  Ross E. Swaney

    IPC: D21B1/16

    CPC classification number: D21B1/16 ,  D21C1/02 ,  D21C5/005 ,  D21H11/00 ,  D21H11/10

    Abstract: In a new process for preparing pulped wood chips for paper making, chips from a hardwood such as eucalyptus are inoculated with aliving culture of one or more white rot fungi. The fungi propagate throughout the body of the wood chip, selectively attacking the lignin of the wood without harming the cellulosic fibers. Subsequent mechanical pulpting results in reduced utilization of energy, improved strength, and reduced cooking time.

    Abstract translation: 在用于制备用于造纸的制浆木片的新方法中，来自诸如桉树的硬木的切片通过一种或多种白腐真菌的活化培养物接种。 真菌遍布整个木片的主体，选择性地攻击木材的木质素，而不损害纤维素纤维。 随后的机械打浆导致能量利用率降低，强度提高，烹饪时间缩短。

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