公开(公告)号：US08513066B2

公开(公告)日：2013-08-20

申请号：US11257973

申请日：2005-10-25

Applicant: Leo Mathew ,  Rode R. Mora

Inventor： Leo Mathew ,  Rode R. Mora

IPC: H01L21/00 ,  H01L21/84

CPC classification number: H01L27/1104 ,  H01L21/823431 ,  H01L27/11 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for creating an inverse T field effect transistor is provided. The method includes creating a horizontal active region and a vertical active region on a substrate. The method further comprises forming a sidewall spacer on a first side of the vertical active region and a second side of the vertical active region. The method further includes removing a portion of the horizontal active region, which is not covered by the sidewall spacer. The method further includes removing the sidewall spacer. The method further includes forming a gate dielectric over at least a first part of the horizontal active region and at least a first part of the vertical active region. The method further includes forming a gate electrode over the gate dielectric. The method further includes forming a source region and a drain region over at least a second part of the horizontal active region and at least a second part of the vertical active region.

Abstract translation: 提供了一种用于产生逆T场效应晶体管的方法。 该方法包括在衬底上创建水平有源区和垂直有源区。 该方法还包括在垂直有源区的第一侧和垂直有源区的第二侧上形成侧壁间隔物。 该方法还包括移除未被侧壁间隔物覆盖的水平有源区的一部分。 该方法还包括去除侧壁间隔物。 该方法还包括在水平有源区域的至少第一部分和垂直有源区域的至少第一部分上形成栅极电介质。 该方法还包括在栅极电介质上形成栅电极。 该方法还包括在水平有源区域的至少第二部分和垂直有源区域的至少第二部分上形成源极区域和漏极区域。

公开(公告)号：US08498140B2

公开(公告)日：2013-07-30

申请号：US12681289

申请日：2008-10-01

Applicant: Jerry G. Fossum ,  Leo Mathew ,  Michael Sadd ,  Vishal P. Trivedi

Inventor： Jerry G. Fossum ,  Leo Mathew ,  Michael Sadd ,  Vishal P. Trivedi

IPC: G11C5/02 ,  G11C5/06 ,  G11C7/00 ,  G11C11/401 ,  G11C11/4063 ,  G11C11/40

CPC classification number: H01L27/108 ,  G11C11/404 ,  G11C2211/4016 ,  H01L27/10802 ,  H01L27/10826 ,  H01L29/7841 ,  H01L29/785

Abstract: Embodiments relate to a two-transistor (2T) floating-body cell (FBC) for embedded-DRAM applications. Further embodiments pertain to a floating-body/gate cell (FBGC), which yields reduction in power dissipation, in addition to better signal margin, longer data retention, and higher memory density.

Abstract translation: 实施例涉及用于嵌入式DRAM应用的双晶体管（2T）浮体单元（FBC）。 除了更好的信号余量，更长的数据保持和更高的存储器密度之外，其它实施例涉及浮体/栅极单元（FBGC），其产生功率损耗的降低。

公开(公告)号：US08076215B2

公开(公告)日：2011-12-13

申请号：US12467035

申请日：2009-05-15

Applicant: Leo Mathew ,  Dharmesh Jawarani

Inventor： Leo Mathew ,  Dharmesh Jawarani

IPC: H01L21/3205

CPC classification number: H01L31/1804 ,  H01L31/1896 ,  Y02E10/547 ,  Y02P70/521

Abstract: A method of forming an electronic device can include forming a patterned layer adjacent to a side of a substrate including a semiconductor material. The method can also include separating a semiconductor layer and the patterned layer from the substrate, wherein the semiconductor layer is a portion of the substrate.

Abstract translation: 形成电子器件的方法可以包括形成与包括半导体材料的衬底的一侧相邻的图案化层。 该方法还可以包括从衬底分离半导体层和图案化层，其中半导体层是衬底的一部分。

公开(公告)号：US07727829B2

公开(公告)日：2010-06-01

申请号：US11671567

申请日：2007-02-06

Applicant: Vishal P. Trivedi ,  Leo Mathew

Inventor： Vishal P. Trivedi ,  Leo Mathew

IPC: H01L21/336

CPC classification number: H01L29/6653 ,  H01L21/2652 ,  H01L29/665

Abstract: A semiconductor device is formed using a semiconductor substrate. A gate dielectric is formed over the semiconductor substrate. A gate electrode layer is formed over the gate dielectric. A patterned masking layer is formed over the gate electrode layer. A first region of the gate electrode layer lies within an opening in the patterned masking layer. The first region of the gate electrode layer is partially etched to leave an elevated portion of the gate electrode layer and a lower portion adjacent to the elevated portion. A sidewall spacer is formed adjacent to the elevated portion and over the lower portion. An implant is performed into the semiconductor substrate using the elevated portion and the sidewall spacer as a mask. The sidewall spacer and the lower portion are removed.

Abstract translation: 使用半导体衬底形成半导体器件。 在半导体衬底上形成栅极电介质。 栅极电极层形成在栅极电介质上。 在栅极电极层上形成图案化掩模层。 栅极电极层的第一区域位于图案化掩模层的开口内。 栅极电极层的第一区域被部分蚀刻以留下栅极电极层的升高部分和邻近升高部分的下部。 侧壁间隔件邻近提升部分并在下部形成。 使用升高部分和侧壁间隔物作为掩模将植入物进行到半导体衬底中。 去除侧墙和下部。

公开(公告)号：US20090280588A1

公开(公告)日：2009-11-12

申请号：US12435947

申请日：2009-05-05

Applicant: Leo Mathew ,  Dharmesh Jawarani

Inventor： Leo Mathew ,  Dharmesh Jawarani

IPC: H01L21/3205 ,  H01L31/02 ,  H01L33/00 ,  H01L21/20

CPC classification number: H01L21/3063 ,  C25F3/30 ,  H01L21/02002 ,  H01L21/7806 ,  H01L31/1892 ,  H01L33/0079 ,  H01L2924/0002 ,  Y02E10/50 ,  H01L2924/00

Abstract: A method of forming an electronic device can include forming a metallic layer over a side of a workpiece including a substrate, a differential etch layer, and a semiconductor layer. The differential etch layer may lie between the substrate and the semiconductor layer, and the semiconductor layer may lie along the side of the workpiece. The process can further include selectively removing at least a majority of the differential etch layer from between the substrate and the semiconductor layer, and separating the semiconductor layer and the metallic layer from the substrate. The selective removal can be performed using a wet etching, dry etching, or electrochemical technique. In a particular embodiment, the same plating bath may be used for plating the metallic layer and selectively removing the differential etch layer.

Abstract translation: 形成电子器件的方法可以包括在包括衬底，差分蚀刻层和半导体层的工件的侧面上形成金属层。 差分蚀刻层可以位于衬底和半导体层之间，并且半导体层可以沿着工件的侧面。 该工艺还可以包括从衬底和半导体层之间选择性地去除差分蚀刻层的至少大部分，以及从衬底分离半导体层和金属层。 可以使用湿蚀刻，干法蚀刻或电化学技术来进行选择性去除。 在特定实施例中，可以使用相同的镀浴来镀覆金属层并选择性地去除差分蚀刻层。

公开(公告)号：US07612619B2

公开(公告)日：2009-11-03

申请号：US11387595

申请日：2006-03-23

Applicant: Mohamed S. Moosa ,  Leo Mathew ,  Sriram S. Kalpat

Inventor： Mohamed S. Moosa ,  Leo Mathew ,  Sriram S. Kalpat

IPC: H03L7/00

CPC classification number: H03D13/00

Abstract: A device and method for phase detection are disclosed. The device includes a phase differential module that provides a phase difference signal based on the phase difference between a data signal and a reference signal. The phase difference signal is provided to a first gate of a multi-gate fin-type field effect transistor (multi-gate FinFET) of the device. A second gate of the multi-gate FinFET transistor receives a bias signal that provides a phase detection threshold. A phase adjustment signal is provided at one or both of the FinFET current electrodes based on the phase difference signal and the bias signal.

Abstract translation: 公开了一种用于相位检测的装置和方法。 该装置包括相位差模块，该相位差模块基于数据信号和参考信号之间的相位差提供相位差信号。 相位差信号被提供给器件的多栅极鳍型场效应晶体管（多栅极FinFET）的第一栅极。 多栅极FinFET晶体管的第二栅极接收提供相位检测阈值的偏置信号。 基于相位差信号和偏置信号，在FinFET电流电极的一个或两个处提供相位调整信号。

公开(公告)号：US07573114B2

公开(公告)日：2009-08-11

申请号：US12201074

申请日：2008-08-29

Applicant: Leo Mathew ,  Michael G. Khazhinsky

Inventor： Leo Mathew ,  Michael G. Khazhinsky

IPC: H01L29/861 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/075 ,  H01L31/105 ,  H01L31/117

CPC classification number: H01L27/0811 ,  H01L29/0657 ,  H01L29/42312 ,  H01L29/7391 ,  H01L29/785

Abstract: An electronic device can include a gated diode, wherein the gated diode includes a junction diode structure including a junction. A first conductive member spaced apart from and adjacent to the junction can be connected to a first signal line. A second conductive member, spaced apart from and adjacent to the junction, can be both electrically connected to a second signal line and electrically insulated from the first conductive member. The junction diode structure can include a p-n or a p-i-n junction. A process for forming the electronic device is also described.

Abstract translation: 电子设备可以包括门控二极管，其中门控二极管包括包括结的结二极管结构。 与结点隔开并相邻的第一导电构件可连接到第一信号线。 与结点间隔开并与其相邻的第二导电构件可以电连接到第二信号线并与第一导电构件电绝缘。 结二极管结构可以包括p-n或p-i-n结。 还描述了用于形成电子设备的过程。

公开(公告)号：US20090093108A1

公开(公告)日：2009-04-09

申请号：US12244413

申请日：2008-10-02

Applicant: Dharmesh Jawarani ,  John R. Alvis ,  Michael G. Harrison ,  Leo Mathew ,  John E. Moore ,  Rode R. Mora

Inventor： Dharmesh Jawarani ,  John R. Alvis ,  Michael G. Harrison ,  Leo Mathew ,  John E. Moore ,  Rode R. Mora

IPC: H01L21/28

CPC classification number: H01L21/28518 ,  H01L21/2855

Abstract: A semiconductor fabrication process includes forming a gate electrode (112) overlying a gate dielectric (114) overlying a semiconductor substrate (104) of a wafer (101) and a liner dielectric layer (116) including vertical portions (118) adjacent sidewalls of the gate electrode and horizontal portions (117) overlying an upper surface of the semiconductor substrate (104). A spacer (108) is formed adjacent a vertical portion (118) and overlying a horizontal portion (117) of the liner dielectric layer (116). After forming the spacer (108), exposed portions of the liner dielectric layer (116) are removed to form a liner dielectric structure (126) covered by the extension spacer (108). The extension spacer (108) is then etched back to expose or uncover extremities of the liner dielectric structure (126). Prior to etching back the spacer (108), a metal (130) may be sputtered deposited over the wafer (101) preparatory to forming a silicide (134). After the etch back the wafer (101) may be dipped in piranha solution and cleaned with an RF sputter (140) of argon.

Abstract translation: 半导体制造工艺包括形成覆盖在晶片（101）的半导体衬底（104）上的栅极电介质（114）上的栅电极（112）和包括垂直部分（118）的衬垫电介质层（116） 栅电极和覆盖在半导体衬底（104）的上表面上的水平部分（117）。 邻近垂直部分（118）并且覆盖衬里介电层（116）的水平部分（117）形成间隔物（108）。 在形成间隔物（108）之后，去除衬里电介质层（116）的暴露部分以形成被延伸间隔物（108）覆盖的衬里电介质结构（126）。 然后将延伸垫片（108）回蚀刻以露出或揭开衬垫介质结构（126）的四肢。 在蚀刻回间隔物（108）之前，金属（130）可以溅射沉积在晶片（101）上，准备形成硅化物（134）。 在蚀刻之后，晶片（101）可以浸入食人鱼溶液中并用氩气的RF溅射（140）清洁。

公开(公告)号：US07446006B2

公开(公告)日：2008-11-04

申请号：US11226826

申请日：2005-09-14

Applicant: Dharmesh Jawarani ,  John R. Alvis ,  Michael G. Harrison ,  Leo Mathew ,  John E. Moore ,  Rode R. Mora

Inventor： Dharmesh Jawarani ,  John R. Alvis ,  Michael G. Harrison ,  Leo Mathew ,  John E. Moore ,  Rode R. Mora

IPC: H01L21/336

CPC classification number: H01L21/28518 ,  H01L21/2855

Abstract: A semiconductor fabrication process includes forming a gate electrode (112) overlying a gate dielectric (114) overlying a semiconductor substrate (104) of a wafer (101) and a liner dielectric layer (116) including vertical portions (118) adjacent sidewalls of the gate electrode and horizontal portions (117) overlying an upper surface of the semiconductor substrate (104). A spacer (108) is formed adjacent a vertical portion (118) and overlying a horizontal portion (117) of the liner dielectric layer (116). After forming the spacer (108), exposed portions of the liner dielectric layer (116) are removed to form a liner dielectric structure (126) covered by the extension spacer (108). The extension spacer (108) is then etched back to expose or uncover extremities of the liner dielectric structure (126). Prior to etching back the spacer (108), a metal (130) may be sputtered deposited over the wafer (101) preparatory to forming a silicide (134). After the etch back the wafer (101) may be dipped in piranha solution and cleaned with an RF sputter (140) of argon.

Abstract translation: 半导体制造工艺包括形成覆盖在晶片（101）的半导体衬底（104）上的栅极电介质（114）上的栅电极（112）和包括垂直部分（118）的衬垫电介质层（116） 栅电极和覆盖在半导体衬底（104）的上表面上的水平部分（117）。 邻近垂直部分（118）并且覆盖衬里介电层（116）的水平部分（117）形成间隔物（108）。 在形成间隔物（108）之后，去除衬里电介质层（116）的暴露部分以形成被延伸间隔物（108）覆盖的衬里电介质结构（126）。 然后将延伸垫片（108）回蚀刻以露出或揭开衬垫介质结构（126）的四肢。 在蚀刻回间隔物（108）之前，金属（130）可以溅射沉积在晶片（101）上，准备形成硅化物（134）。 在蚀刻之后，晶片（101）可以浸入食人鱼溶液中并用氩气的RF溅射（140）清洁。

公开(公告)号：US07439791B2

公开(公告)日：2008-10-21

申请号：US11344511

申请日：2006-01-31

Applicant: Mohamed S. Moosa ,  Sriram S. Kalpat ,  Leo Mathew

Inventor： Mohamed S. Moosa ,  Sriram S. Kalpat ,  Leo Mathew

IPC: H01L35/00

CPC classification number: H03K17/145 ,  H01L29/785 ,  H03K17/687

Abstract: A device and method for temperature compensation of an electronic device are disclosed. The device includes a temperature bias controller with a temperature sensor. A bias signal based upon a signal from the temperature sensor is provided to a first gate of a multiple fin gate field effect transistor (multigate FinFET) transistor of a functional block. A second gate of the multigate FinFET transistor receives a control signal to control its operation within the functional block. In this configuration the first gate of the multigate FinFET transistor can be used for temperature compensation while the second gate is used for functional operation of the transistor. Specific embodiments of the present disclosure will be better understood with respect to the figures.

Abstract translation: 公开了一种用于电子设备的温度补偿的装置和方法。 该装置包括具有温度传感器的温度偏差控制器。 基于来自温度传感器的信号的偏置信号被提供给功能块的多鳍栅极场效应晶体管（多栅极FinFET）晶体管的第一栅极。 多栅极FinFET晶体管的第二栅极接收控制信号以控制其在功能块内的操作。 在该配置中，多栅极FinFET晶体管的第一栅极可用于温度补偿，而第二栅极用于晶体管的功能操作。 将更好地理解本发明的具体实施方式。