Electronic systems comprising a system bus
    251.
    发明申请
    Electronic systems comprising a system bus 审中-公开
    包括系统总线的电子系统

    公开(公告)号:US20040193836A1

    公开(公告)日:2004-09-30

    申请号:US10701384

    申请日:2003-11-04

    CPC classification number: G06F13/385

    Abstract: A resynchronization module for use in an electronic system comprising a system bus comprises pipeline means of for pipelining the transactions intended for and/or originating from the associated functional module. The pipeline means comprise a first buffer circuit and at least one second buffer circuit, which are connected in parallel, and are each, adapted for storing transaction data of a specific transaction.

    Abstract translation: 用于包括系统总线的电子系统的再同步模块包括用于流水线化用于和/或源自相关联的功能模块的事务的流水线装置。 流水线装置包括并联连接的第一缓冲电路和至少一个第二缓冲电路,并且各自适于存储特定事务的交易数据。

    Integrated circuit comprising a voltage generator and a circuit limiting the voltage supplied by the voltage generator
    252.
    发明申请
    Integrated circuit comprising a voltage generator and a circuit limiting the voltage supplied by the voltage generator 有权
    集成电路包括电压发生器和限制由电压发生器提供的电压的电路

    公开(公告)号:US20040164788A1

    公开(公告)日:2004-08-26

    申请号:US10721058

    申请日:2003-11-24

    Inventor: Jean Devin

    CPC classification number: H02H9/046

    Abstract: An integrated circuit having a voltage generator supplying a determined voltage, a voltage-limiting circuit arranged at the output of the voltage generator, the voltage-limiting circuit having at least one PN junction formed by a diode-arranged MOS transistor, the PN junction having a breakdown voltage defining a threshold for triggering the voltage-limiting circuit as from which the PN junction is on by avalanche effect, at least one load in series with the PN junction for limiting an avalanche current passing through the PN junction when the PN junction is on, and at least one switch in parallel with the PN junction and the load, the switch arranged in the open state when the PN junction is off and to be in the closed state when the PN junction is on.

    Abstract translation: 一种具有提供确定电压的电压发生器的集成电路,布置在电压发生器的输出端的限压电路,该限压电路具有由二极管配置的MOS晶体管形成的至少一个PN结,该PN结具有 限定阈值的击穿电压,用于触发由PN结接通的雪崩效应的电压限制电路,与PN结串联的至少一个负载,用于限制当PN结处于PN结处时通过PN结的雪崩电流 以及与PN结和负载并联的至少一个开关,当PN结关闭时,开关布置成处于断开状态,并且当PN结接通时处于闭合状态。

    Method of controlling a switch mode power supply having only one inductive element and several outputs and corresponding power supply
    253.
    发明申请
    Method of controlling a switch mode power supply having only one inductive element and several outputs and corresponding power supply 有权
    控制只有一个电感元件和多个输出和相应电源的开关模式电源的方法

    公开(公告)号:US20040160715A1

    公开(公告)日:2004-08-19

    申请号:US10726259

    申请日:2003-12-02

    CPC classification number: H02M3/157 H02M3/1584 Y10T307/696 Y10T307/702

    Abstract: The switch mode power supply includes a switching cell SC controllable cyclically and including only one inductive element L and several individually selectable outputs. During each conduction cycle, a total power level corresponding to the sum of the individual power levels respectively required by all the outputs OUTi during this cycle is injected into the inductive element L, the outputs requiring a non-zero individual power level are selected successively and in a predetermined order that is identical for all the cycles, and, at each selected output, the corresponding individual power level is produced.

    Abstract translation: 开关模式电源包括周期性可控的切换单元SC,并且仅包括一个电感元件L和几个可单独选择的输出。 在每个导通周期期间,对应于在该周期期间所有输出OUTi分别要求的各个功率电平之和的总功率电平被注入到电感元件L中,连续选择需要非零个别功率电平的输出, 以对于所有周期相同的预定顺序,并且在每个选择的输出处产生相应的单独功率电平。

    Method and circuit for correcting the offset of an amplification chain
    254.
    发明申请
    Method and circuit for correcting the offset of an amplification chain 有权
    用于校正放大链偏移的方法和电路

    公开(公告)号:US20040155703A1

    公开(公告)日:2004-08-12

    申请号:US10765767

    申请日:2004-01-26

    CPC classification number: H03H19/004 H03F1/304

    Abstract: A circuit for correcting the offset of an amplification and filtering chain having a predetermined gain and cut-off frequency depending on the value of at least one capacitor, comprising: a correction means for subtracting from the chain input a correction signal depending on the value of a programmable digital word; a digital automaton for, in a setting phase, searching, then memorizing one of two consecutive values of the digital word between which the output signal of the chain switches sign, the input signal being canceled during a setting phase; and comprising a means for, during the setting phase, reducing the value of said at least one capacitor with respect to its normal operating value.

    Abstract translation: 一种用于根据至少一个电容器的值校正具有预定增益和截止频率的放大和滤波链的偏移的电路,包括:校正装置,用于从链输入中减去校正信号,该校正信号取决于 可编程数字字; 一个数字自动机,用于在设定阶段中搜索,然后存储所述数字字的两个连续值中的一个,所述数字字的输出信号在所述数字字的两个连续值之间,所述输入信号在设定阶段被取消; 并且包括用于在设定阶段期间相对于其正常工作值减小所述至少一个电容器的值的装置。

    Generation of a guard interval in a DMT modulation transmission
    255.
    发明申请
    Generation of a guard interval in a DMT modulation transmission 有权
    在DMT调制传输中产生保护间隔

    公开(公告)号:US20040151110A1

    公开(公告)日:2004-08-05

    申请号:US10761708

    申请日:2004-01-21

    CPC classification number: H04L27/2607 H04L27/2628

    Abstract: A circuit for generating a cyclic prefix of a symbol comprised of a sequence of time samples, the prefix being the reproduction of the last samples of the symbol at the beginning of the symbol, the symbol being obtained by inverse Fourier transform of complex coefficients corresponding to respective frequencies. The circuit includes a multiplier that shifts the phase of each complex coefficient by a value proportional to its frequency, a memory for storing the samples at the beginning of the symbol, and a multiplexer that copies at the end of the symbol the stored samples.

    Abstract translation: 一种用于产生由时间序列序列构成的符号的循环前缀的电路,该前缀是在符号开始处的符号的最后样本的再现,该符号是通过对应于 各自的频率。 该电路包括乘法器,该乘法器将每个复系数的相位与其频率成比例的值移位,用于存储符号开始处的采样的存储器以及在符号结尾处复制存储的采样的多路复用器。

    Control circuit of two current unidirectional switches
    256.
    发明申请
    Control circuit of two current unidirectional switches 有权
    两个电流单向开关的控制电路

    公开(公告)号:US20040135618A1

    公开(公告)日:2004-07-15

    申请号:US10698809

    申请日:2003-10-31

    Inventor: Benoit Peron

    Abstract: A circuit for controlling two switches assembled in anti-parallel, comprising in series between two terminals of the anti-parallel assembly, two identical control stages respectively dedicated to each switch and between which is interposed a common impedance setting a phase angle for the turning-on of the switches, each stage comprising: a controllable current source for providing a current to a control electrode of the concerned switch; a capacitor for storing a supply voltage of at least the current source; an element of activation/deactivation of a the current source according to the voltage across the stage capacitor; and an assembly for discharging the capacitor.

    Abstract translation: 一种用于控制反并联组装的两个开关的电路,包括串联在反并联组件的两个端子之间的两个相同的控制级,分别专用于每个开关,并且其间设置有公共阻抗, 每个级包括:用于向相关开关的控制电极提供电流的可控电流源; 用于存储至少所述电流源的电源电压的电容器; 根据两级电容器两端的电压激活/去激活电流源的元件; 以及用于放电电容器的组件。

    Decimal set point clock generator and application of this clock generator to a uart circuit
    257.
    发明申请
    Decimal set point clock generator and application of this clock generator to a uart circuit 有权
    十进制设定点时钟发生器和该时钟发生器应用于uart电路

    公开(公告)号:US20040130361A1

    公开(公告)日:2004-07-08

    申请号:US10684823

    申请日:2003-10-14

    CPC classification number: G06F1/08

    Abstract: A programmable clock generator delivers, using a primary clock signal of determined frequency, a first clock signal the frequency of which is equal to the frequency of the primary clock signal divided by a set point M. The set point M is a decimal number comprising a whole part M1 and a decimal part M2 and the clock generator modulates the period of the pulses of the first clock signal so that the duration of Ni successive pulses is substantially equal to M*Ni times the period of the primary clock signal, Ni being a reference number for modulating the period of the pulses of the first clock signal.

    Abstract translation: 可编程时钟发生器使用确定频率的主时钟信号来传送其频率等于主时钟信号除以设定点M的频率的第一时钟信号。设定点M是十进制数,包括 整个部分M1和小数部分M2,并且时钟发生器调制第一时钟信号的脉冲的周期,使得Ni连续脉冲的持续时间基本上等于主时钟信号的周期的M * Ni,Ni是主时钟信号的周期 用于调制第一时钟信号的脉冲周期的参考号。

    Communication between electromagnetic transponders
    258.
    发明申请
    Communication between electromagnetic transponders 有权
    电磁转发器之间的通讯

    公开(公告)号:US20040104809A1

    公开(公告)日:2004-06-03

    申请号:US10712325

    申请日:2003-11-12

    CPC classification number: G06K19/0723

    Abstract: An electromagnetic transponder intended to draw the power necessary to its operation of from a field radiated by a terminal of transmission of a carrier at a first supply frequency and to back-modulate the received signal at the rate of a sub-carrier at a second frequency lower than the first one, and comprising means capable of demodulating and decoding signals modulated by said sub-carrier, as well as a system of communication between such transponders.

    Abstract translation: 一种电磁转发器,用于从第一电源频率的载波发射终端辐射的场中获取其工作所需的功率,并以第二频率以副载波的速率对接收信号进行后向调制 低于第一个,并且包括能够解调和解码由所述子载波调制的信号的装置以及这种应答器之间的通信系统。

    Transformation of a periodic signal into an adjustable-frequency signal
    259.
    发明申请
    Transformation of a periodic signal into an adjustable-frequency signal 有权
    将周期性信号转换成可调频率信号

    公开(公告)号:US20040056690A1

    公开(公告)日:2004-03-25

    申请号:US10662180

    申请日:2003-09-12

    Abstract: A device for transforming a periodic input signal into an output signal of distinct frequency, comprising two adjustable delay means receiving the input signal, a multiplexer selecting the output signal of one or the other of the delay means, control means for, according to whether the output signal frequency must be smaller or greater than the input signal frequency, increasing or decreasing at the rate of the input signal, or at a multiple of this rate, the delay of the selected delay means, and controlling a minimum or maximum delay for the delay means which has not been selected, and a phase comparator adapted to changing the multiplexer selection when the transitions of the signals output by the delay means corresponding to a same transition of the input signal are offset by a duration greater than or equal to one period of the input signal.

    Abstract translation: 一种用于将周期性输入信号变换为不同频率的输出信号的装置,包括接收输入信号的两个可调延迟装置,选择延迟装置中的一个或另一个的输出信号的多路复用器,根据是否 输出信号频率必须小于或大于输入信号频率,以输入信号的速率增加或减小,或以该速率的倍数,所选择的延迟装置的延迟,并且控制最小或最大延迟 延迟装置,以及相位比较器,适于在延迟装置输出的对应于输入信号的相同转变的信号的转变偏移持续时间大于或等于一个周期的情况下改变多路复用器选择 的输入信号。

    Vertical power component manufacturing method
    260.
    发明申请
    Vertical power component manufacturing method 有权
    垂直功率元件制造方法

    公开(公告)号:US20030219964A1

    公开(公告)日:2003-11-27

    申请号:US10423359

    申请日:2003-04-25

    Inventor: Mathieu Roy

    Abstract: A method for manufacturing a vertical power component on a substrate formed of a lightly-doped silicon wafer, including the steps of boring on the lower surface side of the substrate a succession of holes perpendicular to this surface; diffusing a dopant from the holes, of a second conductivity type opposite to that of the substrate; and boring similar holes on the upper surface side of the substrate to define an isolating wall and diffuse from these holes a dopant of the second conductivity type with a high doping level, the holes corresponding to the isolating wall being sufficiently close for the diffused areas to join laterally and vertically.

    Abstract translation: 一种在由轻掺杂硅晶片形成的基板上制造垂直功率分量的方法,包括以下步骤:在所述基板的下表面侧镗孔垂直于该表面的一连串孔; 扩散与孔相反的第二导电类型的掺杂剂; 并且在衬底的上表面侧上钻出类似的孔,以限定隔离壁并且从这些孔扩散具有高掺杂水平的第二导电类型的掺杂剂,对应于隔离壁的孔对于扩散区域是足够接近的 横向和垂直连接。

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