公开(公告)号：US20240045815A1

公开(公告)日：2024-02-08

申请号：US18365031

申请日：2023-08-03

Applicant: STMicroelectronics (Alps) SAS

Inventor： Jawad Benhammadi

IPC: G06F13/16 ,  G06F13/40 ,  G06F12/1045

CPC classification number: G06F13/1668 ,  G06F13/4063 ,  G06F12/1063

Abstract: A FLASH memory device includes a FLASH memory having an array of non-volatile memory cells and a volatile memory. A FLASH memory interface is arranged outside of the FLASH memory, and a first communication bus couples the FLASH memory interface to the array of memory cells. A second communication bus couples the FLASH memory interface to the volatile memory.

公开(公告)号：US11888208B2

公开(公告)日：2024-01-30

申请号：US17408982

申请日：2021-08-23

Applicant: STMicroelectronics (Alps) SAS

Inventor： Deborah Cogoni

IPC: H01Q9/04 ,  H01Q1/12 ,  H01Q1/38

CPC classification number: H01Q1/12 ,  H01Q1/38

Abstract: An electronic device includes a first layer with an antenna and a second metal layer that extends over the entire first layer. The second metal layer includes at least one laterally-closed cavity that is located vertically above the antenna. The cavity is filled, at least in part, by a resin material. A first plate supporting a second metal plate extends over the cavity with the second metal plate positioned vertically above the antenna. The first metal plate may be supported by a ledge within the cavity. Alternatively, the second metal plate is embedded in the resin filling the cavity, with the second metal plate positioned vertically above the antenna.

公开(公告)号：US11876366B2

公开(公告)日：2024-01-16

申请号：US18062980

申请日：2022-12-07

Applicant: STMicroelectronics (Alps) SAS

Inventor： Michel Bouche

IPC: H02H3/20 ,  H02H3/02 ,  H02H3/033

CPC classification number: H02H3/202 ,  H02H3/021 ,  H02H3/033 ,  H02H3/20

Abstract: An embodiment of the present disclosure relates to an electronic circuit including a first switch coupling a first node of the circuit to an input/output terminal of the circuit; a second switch coupling the first node to a second node of application of a fixed potential; and a high-pass filter having an input coupled to the terminal and an output coupled to a control terminal of the second switch.

公开(公告)号：US20230317748A1

公开(公告)日：2023-10-05

申请号：US18129993

申请日：2023-04-03

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Alps) SAS

Inventor： Jonathan STECKEL ,  Emmanuel JOSSE ,  Eric MAZALEYRAT ,  Youness RADID

IPC: H01L27/146

CPC classification number: H01L27/14621 ,  H01L27/14627 ,  H01L27/14612 ,  H01L27/14636

Abstract: An imaging device includes an array of photosensors. A film of semiconductor nanoparticles is common to the photosensors of the array. The nanoparticles are configured to be excited by light with wavelengths in a range from 280 to 1500 nanometers. Each photosensor includes a top electrode and a bottom electrode positioned on opposite sides of the film of semiconductor nanoparticles. At least some of the photosensors further include a filter configured to transmit light with wavelengths in a range from 280 to 400 nanometers, and to at least partially filter out light with wavelengths greater than 400 nanometers from reaching the photosensor. A transistor level is electrically coupled to the top and bottom electrodes of the photosensors.

公开(公告)号：US20230291366A1

公开(公告)日：2023-09-14

申请号：US18174213

申请日：2023-02-24

Applicant: STMicroelectronics (Alps) SAS ,  STMicroelectronics (Grenoble) SAS

Inventor： Vratislav Michal ,  Nicolas Moeneclaey ,  Jean-Luc Patry

IPC: H03F3/08 ,  H03F3/45

CPC classification number: H03F3/087 ,  H03F3/45475 ,  H03F2203/45288

Abstract: The present disclosure relates to a device comprising a first transimpedance amplifier comprising a first amplification stage with a first MOS transistor, a second transimpedance amplifier comprising a second amplification stage with a second MOS transistor, and a current source series-connected with the first and second amplification stages, the current source having a first terminal coupled to the drain of the first MOS transistor and a second terminal coupled to the drain of the second MOS transistor.

公开(公告)号：US20230184938A1

公开(公告)日：2023-06-15

申请号：US18062517

申请日：2022-12-06

Applicant: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED ,  STMICROELECTRONICS (GRENOBLE 2) SAS ,  STMICROELECTRONICS (ALPS) SAS

Inventor： Joseph HANNAN ,  Adam CALEY ,  Megane Estelle GUILLON ,  Charlotte MILANETTO ,  Christophe PREMONT

IPC: G01S17/08 ,  G01S7/481

CPC classification number: G01S17/08 ,  G01S7/4813

Abstract: The present disclosure relates to an assembly for an electronic device, the assembly comprising: a display screen comprising a plurality of pixels arranged in a matrix scheme comprising rows orientated in a first direction and columns orientated in a second direction; and a proximity sensor comprising at least one optical light emitter, each adapted to emit a light beam through one or more first pixels of the display screen, and an optical detector adapted to receive through one or more second pixels of the display screen the light beam emitted by the at least one optical light emitter and reflected on an object; wherein none of the one or more second pixels is in the same row as any of the one or more first pixels, and none of the one or more second pixels is in the same column as any of the one or more first pixels.

公开(公告)号：US20230154919A1

公开(公告)日：2023-05-18

申请号：US17969867

申请日：2022-10-20

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Alps) SAS

Inventor： Nicolas Moeneclaey ,  Jean-Luc Patry

IPC: H01L27/02

CPC classification number: H01L27/0255 ,  H01L27/0288 ,  H01L27/0262

Abstract: In embodiments, an integrated circuit is provided that includes an input/output cell having a first signal terminal and a second signal terminal connected to a domain and capable of withstanding a maximum voltage greater than the power supply voltage. The input/output cell further includes an array of N diodes coupled in series between the second signal terminal and a cold power supply point. The array has an overall threshold voltage greater than the maximum voltage. The integrated circuit further includes a control circuit connected between the first signal terminal and the array of diodes. The control circuit is configured, in the presence of a second voltage on the first signal terminal greater than the maximum voltage, to automatically and autonomously short-circuit at least one of the diodes in the array to limit the voltage on the second signal terminal to a third voltage less than the maximum voltage.

公开(公告)号：US20230069969A1

公开(公告)日：2023-03-09

申请号：US17903280

申请日：2022-09-06

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Alps) SAS

Inventor： Younes BOUTALEB ,  Laurent SCHWARTZ

IPC: H01L23/367 ,  H01L23/00 ,  H01L25/065 ,  H01L23/373

Abstract: A package for integrated circuits includes a base substrate having a mounting face. A first electronic chip has a top face electrically connected to the mounting face and a bottom face mounted to the mounting face by an adhesive layer. A second electronic chip has a bottom face covered with a thermal interface layer and a top face electrically connected to the mounting face. A heat sink includes a first part embedded in the adhesive layer, a second part having a bottom face in contact with the layer of thermal interface material and a top face, and a connection part between the first part and the second part. A coating encapsulates the first and second electronic chips and the heat sink. The top face of the second part of the heat sink exposed from the encapsulating coating.

公开(公告)号：US20220415822A1

公开(公告)日：2022-12-29

申请号：US17847330

申请日：2022-06-23

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Alps) SAS

Inventor： Claire LAPORTE ,  Laurent SCHWARTZ ,  Godfrey DIMAYUGA

IPC: H01L23/552 ,  H01L23/498

Abstract: A support substrate has a mounting face and a connection face opposite to the mounting face. An electronic chip is mounted to the mounting face and a matrix of connectors is mounted to the connection face. The support substrate includes an interconnection structure formed by a pair of conductive interconnection tracks that electrically connect the electronic chip to the matrix of connectors and circulate differential signals. The two interconnection tracks of the pair of conductive interconnection tracks extend facing each other at different depths of the support substrate. An isolation structure in the support substrate laterally isolates the pair of conductive interconnection tracks. Isolation plates above and below the pair of conductive interconnection tracks provide further isolation.

公开(公告)号：US11509332B2

公开(公告)日：2022-11-22

申请号：US17394118

申请日：2021-08-04

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Alps) SAS

Inventor： Fabrice Romain ,  Mathieu Lisart ,  Patrick Arnould

IPC: H03M13/29 ,  G06F11/10

Abstract: A datum is written to a memory, by splitting a binary word, representative of the datum and an error correcting or detecting code, into a first part and a second part. The first part is written at a logical address in a first memory circuit. The second part is written at the logical address in a second memory circuit. The error correcting or detecting code is dependent on both the datum and the logical address.