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公开(公告)号：US11482280B2
公开(公告)日：2022-10-25
申请号：US16436734
申请日：2019-06-10
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Russell L. Meyer , Agostino Pirovano , Andrea Redaelli , Lorenzo Fratin , Fabio Pellizzer
Abstract: Disclosed herein is a memory cell including a memory element and a selector device. Data may be stored in both the memory element and selector device. The memory cell may be programmed by applying write pulses having different polarities and magnitudes. Different polarities of the write pulses may program different logic states into the selector device. Different magnitudes of the write pulses may program different logic states into the memory element. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities and magnitudes of the write pulses.
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公开(公告)号：US20220336005A1
公开(公告)日：2022-10-20
申请号：US17231657
申请日：2021-04-15
Applicant: Micron Technology, Inc.
Inventor： Paolo Fantini , Enrico Varesi , Lorenzo Fratin , Fabio Pellizzer
IPC: G11C11/408 , G11C11/4074 , G11C5/06
Abstract: Methods, systems, and devices for a decoding architecture for memory devices are described. Word line plates of a memory array may each include a sheet of conductive material that includes a first portion extending in a first direction within a plane along with multiple fingers extending in a second direction within the plane. Two word line plates in a same plane may be activated via a shared electrode. Memory cells coupled with the two word line plates sharing the electrode, or a subset thereof, may represent a logical page for accessing memory cells. A memory cell may be accessed via a first voltage applied to a word line plate coupled with the memory cell and a second voltage applied to a pillar electrode coupled with the memory cell. Parallel or simultaneous access operations may be performed for two or more memory cells within a same page of memory cells.
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公开(公告)号：US20220335997A1
公开(公告)日：2022-10-20
申请号：US17231661
申请日：2021-04-15
Applicant: Micron Technology, Inc.
Inventor： Paolo Fantini , Lorenzo Fratin , Fabio Pellizzer , Enrico Varesi
Abstract: Methods, systems, and devices for a decoding architecture for memory devices are described. Word line plates of a memory array may each include a sheet of conductive material that includes a first portion extending in a first direction within a plane along with multiple fingers extending in a second direction within the plane. Memory cells coupled with a word line plate, or a subset thereof, may represent a logical page for accessing memory cells. Each word line plate may be coupled with a corresponding word line driver via a respective electrode. A memory cell may be accessed via a first voltage applied to a word line plate coupled with the memory cell and a second voltage applied to a pillar electrode coupled with the memory cell. Parallel or simultaneous access operations may be performed for two or more memory cells within a same page of memory cells.
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公开(公告)号：US11475951B2
公开(公告)日：2022-10-18
申请号：US17162563
申请日：2021-01-29
Applicant: Micron Technology, Inc.
Inventor： Agostino Pirovano , Fabio Pellizzer
Abstract: The present disclosure includes apparatuses and methods for material implication operations in memory with reduced program voltages. An example apparatus can include an array of memory cells that further includes a first memory cell coupled to a first access line and to a first one of a plurality of second access lines and a second memory cell coupled to the first access line and to a second one of the plurality of second access lines. The circuitry can be configured to apply, across the second memory cell, a first voltage differential having a first polarity and a first magnitude. The first voltage differential reduces, if the second memory cell is programmed to a first data state, a magnitude of a drifted threshold voltage for programming the second memory cell to a second data state. The circuitry is further configured to apply, subsequent to the application of the first voltage differential, a first signal to the first access line. The circuitry is further configured to, while the first signal is being applied to the first access line, apply, subsequent to the application of the first voltage differential, a second voltage differential having a second polarity and the first magnitude across the first memory cell and apply a third voltage differential having the second polarity across the second memory cell. A material implication operation is performed as a result of the first, second, and third voltage differentials applied across the first and the second memory cells with a result of the material implication operation being stored on the second memory cell.
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公开(公告)号：US20220302210A1
公开(公告)日：2022-09-22
申请号：US17431660
申请日：2020-07-22
Applicant: Micron Technology, Inc.
Inventor： Lorenzo Fratin , Paolo Fantini , Fabio Pellizzer
Abstract: Methods for, apparatuses with and vertical 3D memory devices are described. A vertical 3D memory device may comprise: a plurality of contacts associated with a plurality of digit lines and extending through a substrate; a plurality of word line plates separated from one another by respective dielectric layers and including a first plurality of word line plates and a second plurality of word line plates; a first dielectric material positioned between the first plurality and the second plurality of word line plates, the first dielectric material extending in a serpentine shape over the substrate; a conformal material positioned between the first dielectric material and the first and second plurality of word line plates, respectively; a plurality of spacers; a plurality of pillars coupled with the plurality of contacts; and a plurality of storage elements each comprising chalcogenide material positioned in a recess.
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Patent Agency Ranking
公开(公告)号：US20220301619A1
公开(公告)日：2022-09-22
申请号：US17716740
申请日：2022-04-08
Applicant: Micron Technology, Inc.
Inventor： Mattia Robustelli , Fabio Pellizzer , Innocenzo Tortorelli , Agostino Pirovano
Abstract: Methods, systems, and devices for reading a multi-level memory cell are described. The memory cell may be configured to store three or more logic states. The memory device may apply a first read voltage to a memory cell to determine a logic state stored by the memory cell. The memory device may determine whether a first snapback event occurred and apply a second read voltage based on determining that the first snapback event failed to occur based on applying the first read voltage. The memory device may determine whether a second snapback event occurred and determine the logic state based on whether the first snapback event or the second snapback event occurred.
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公开(公告)号：US20220262859A1
公开(公告)日：2022-08-18
申请号：US17735810
申请日：2022-05-03
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Fabio Pellizzer
Abstract: Methods, systems, and devices for a capacitive pillar architecture for a memory array are described. An access line within a memory array may be, include, or be coupled with a pillar. The pillar may include an exterior electrode, such as a hollow exterior electrode, surrounding an inner dielectric material that may further surround an interior, core electrode. The interior electrode may be maintained at a voltage level during at least a portion of an access operation for a memory cell coupled with the pillar. Such a pillar structure may increase a capacitance of the pillar, for example, based on a capacitive coupling between the interior and exterior electrodes. The increased capacitance may provide benefits associated with operating the memory array, such as increased memory cell programming speed, programming reliability, and read disturb immunity.
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公开(公告)号：US11302390B2
公开(公告)日：2022-04-12
申请号：US16926557
申请日：2020-07-10
Applicant: Micron Technology, Inc.
Inventor： Mattia Robustelli , Fabio Pellizzer , Innocenzo Tortorelli , Agostino Pirovano
Abstract: Methods, systems, and devices for reading a multi-level memory cell are described. The memory cell may be configured to store three or more logic states. The memory device may apply a first read voltage to a memory cell to determine a logic state stored by the memory cell. The memory device may determine whether a first snapback event occurred and apply a second read voltage based on determining that the first snapback event failed to occur based on applying the first read voltage. The memory device may determine whether a second snapback event occurred and determine the logic state based on whether the first snapback event or the second snapback event occurred.
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公开(公告)号：US20220059763A1
公开(公告)日：2022-02-24
申请号：US17480694
申请日：2021-09-21
Applicant: Micron Technology, Inc.
Inventor： Agostino Pirovano , Kolya Yastrebenetsky , Anna Maria Conti , Fabio Pellizzer
Abstract: Methods, systems, and devices for memory cells with asymmetrical electrode interfaces are described. A memory cell with asymmetrical electrode interfaces may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a top surface area in contact with a top electrode and a bottom surface area in contact with a bottom electrode, where the top surface area in contact with the top electrode is a different size than the bottom surface area in contact with the bottom electrode.
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公开(公告)号：US11217322B2
公开(公告)日：2022-01-04
申请号：US16990114
申请日：2020-08-11
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Agostino Pirovano , Andrea Redaelli , Fabio Pellizzer , Hongmei Wang
Abstract: Methods, systems, and devices for drift mitigation with embedded refresh are described. A memory cell may be written to and read from using write and read voltages, respectively, that are of different polarities. For example, a memory cell may be written to by applying a first write voltage and may be subsequently read from by applying a first read voltage of a first polarity. At least one additional (e.g., a second) read voltage—a setback voltage—of a second polarity may be utilized to return the memory cell to its original state. Thus the setback voltage may mitigate a shift in the voltage distribution of the cell caused by the first read voltage.
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