公开(公告)号：US20250005457A1

公开(公告)日：2025-01-02

申请号：US18821673

申请日：2024-08-30

Applicant: Intel Corporation

Inventor： Mario Jose Divan Koller ,  Mariano Ortega De Mues ,  Marcos Emanuel Carranza ,  Cesar Ignacio Martinez-Spessot ,  Mateo Guzman ,  Francesc Guim Bernat ,  John Joseph Browne ,  Mats Gustav Agerstam ,  Gavin Bartlett Lewis ,  Abhishek Pillai ,  Tejaswini Sirlapu

IPC: G06N20/00

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed to provide recommendations for device management. An example non-transitory machine readable storage medium comprising instructions to cause programmable circuitry to at least: determine an action to be performed for a plurality of computing devices, the action includes information about the computing devices and an operation to be performed on the computing devices; compare the action with a plurality of prior actions; and report a predicted result based on a similarity of the action with at least one of the plurality of prior actions.

公开(公告)号：US20250005364A1

公开(公告)日：2025-01-02

申请号：US18761714

申请日：2024-07-02

Applicant: Intel Corporation

Inventor： Dmitry Gorokhov ,  Alexander Kozlov

IPC: G06N3/082 ,  G06F18/2113 ,  G06N3/063 ,  G06N5/04

Abstract: Systems, apparatuses and methods may provide for technology that aggregates contextual information from a first network layer in a neural network having a second network layer coupled to an output of the first network layer, wherein the context information is to be aggregated in real-time and after a training of the neural network, and wherein the context information is to include channel values. Additionally, the technology may conduct an importance classification of the aggregated context information and selectively exclude one or more channels in the first network layer from consideration by the second network layer based on the importance classification.

公开(公告)号：US20250005159A1

公开(公告)日：2025-01-02

申请号：US18217484

申请日：2023-06-30

Applicant: INTEL CORPORATION

Inventor： Avinash CHANDRASEKARAN ,  Murugasamy K. NACHIMUTHU ,  Mariusz ORIOL ,  Piotr MATUSZCZAK

IPC: G06F21/57 ,  G06F8/65 ,  G06F21/44

Abstract: An apparatus and method are described for staging and activating microcode of a processor. For example, one embodiment of a processor comprises: a plurality of functional blocks, each functional block operable, at least in part, based on microcode and including a non-volatile memory to store a corresponding microcode update (MCU); a plurality of MCU staging memories, each MCU staging memory to temporarily store one or more of the MCUs for one or more corresponding functional blocks of the plurality of functional blocks; authentication hardware logic to attempt to validate each MCU of the one or more MCUs stored in each MCU staging memory, wherein each MCU is to be copied to a non-volatile memory of a corresponding functional block only after a successful authentication.

公开(公告)号：US20250005138A1

公开(公告)日：2025-01-02

申请号：US18346222

申请日：2023-07-01

Applicant: Intel Corporation

Inventor： Michael LeMay ,  David M. Durham

IPC: G06F21/54 ,  G06F21/78

Abstract: Techniques for explicit integrity check value initialization are described. In an embodiment, an apparatus includes an instruction decoder to decode a single instruction to set an integrity check value ICV corresponding to a destination location in a memory; and execution circuitry coupled to the instruction decoder, the execution circuitry to perform one or more operations corresponding to the single instruction, including storing data indicated by the single instruction into the destination location, and storing the ICV in the memory.

公开(公告)号：US20250005137A1

公开(公告)日：2025-01-02

申请号：US18346220

申请日：2023-07-01

Applicant: Intel Corporation

Inventor： David M. Durham

IPC: G06F21/54 ,  G06F21/55

Abstract: Techniques for instruction tagging for intra-object memory tagging are described. In an embodiment, an apparatus includes an instruction decoder to decode a first instruction having an instruction tag value; and execution circuitry coupled to the instruction decoder, the execution circuitry to perform one or more operations corresponding to the first instruction, including generating a first data tag value based on the instruction tag value and a relative enumeration in a pointer to data.

公开(公告)号：US20250004878A1

公开(公告)日：2025-01-02

申请号：US18539380

申请日：2023-12-14

Applicant: Intel Corporation

Inventor： Yanxin ZHAO ,  Tao XU ,  Yufu LI ,  Shijie LIU ,  Lei ZHU

IPC: G06F11/10

Abstract: A method and system for error check and scrub (ECS) error data collection and reporting for a memory device. A controller includes circuitry and a buffer. The circuitry may be configured to read ECS error data from a register of a memory device and calculate an ECS error increase rate based on the ECS error data. The circuitry may be configured to inform basic input output system (BIOS) by interrupt if a total number of ECS errors reaches or exceeds an ECS error number threshold or if the ECS error increase rate reaches or exceeds an ECS error rate threshold. The controller may be an out-of-band device, e.g., a baseboard management controller or a memory micro controller.

公开(公告)号：US20250004829A1

公开(公告)日：2025-01-02

申请号：US18345280

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Jeroen Leijten

IPC: G06F9/48

Abstract: Techniques for hardware based acceleration of synchronous data flow graphs for data-driven multi-core signal processing systems are described. In certain examples, a system includes a processor comprising a processing circuit to perform a task of a synchronous data flow graph, an input memory for the task of the synchronous data flow graph, an output memory for the task of the synchronous data flow graph, and a synchronous data flow manager circuit to store user-visible state for the input memory and the output memory; and a synchronous data flow functional circuit, coupled to the processor, to cause the processing circuit to perform the task based on the user-visible state from the synchronous data flow manager circuit.

公开(公告)号：US20250004775A1

公开(公告)日：2025-01-02

申请号：US18345909

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Zeshan Chishti ,  Jeffrey Cook ,  Thomas McDonald

IPC: G06F9/38

Abstract: Systems, methods, and apparatuses relating to hardware for auto-predication for loops with dynamically varying iteration counts are disclosed. In an embodiment, a processor core includes a decoder to decode instructions into decoded instructions, an execution unit to execute the decoded instructions, a branch predictor circuit to predict a future outcome of a branch instruction, and a branch predication manager circuit to identify a plurality of popular iteration counts for a loop and to predicate a region including a number of loop iterations equal to one of the plurality of popular iteration counts.

公开(公告)号：US20250004773A1

公开(公告)日：2025-01-02

申请号：US18217428

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Christopher J. HUGHES ,  Zhe WANG ,  Dan BAUM ,  Venkateswara Rao MADDURI ,  Chen DAN ,  Joseph NUZMAN

IPC: G06F9/38 ,  G06F9/30

Abstract: An apparatus and method are described for prefetching data with hints. For example, one embodiment of a processor comprises: a plurality of cores to process instructions; a first core of the plurality of cores comprising: decoder circuitry to decode instructions indicating memory operations including load operations of a first type with shared data hints and load operations of a second type without shared data hints; execution circuitry to execute the instructions to perform the memory operations; data prefetch circuitry to store tracking data in a tracking data structure responsive to the memory operations, a portion of the tracking data associated with the first type of load operations; and the data prefetch circuitry to detect memory access patterns using the tracking data, the data prefetch circuitry to responsively issue one or more prefetch operations using shared data hints based, at least in part, on the portion of the tracking data associated with the first type of load operations.

公开(公告)号：US20250004220A1

公开(公告)日：2025-01-02

申请号：US18346039

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Sufi R. Ahmed ,  Shan Zhong ,  Eric J. M. Moret ,  Yang Wu

IPC: G02B6/42

Abstract: Photonic integrated circuits and optical couplers with improved process tolerance, and methods of forming the same, are disclosed herein. In one example, an integrated circuit package includes a photonic integrated circuit (PIC) to send or receive optical signals and an optical coupler to optically couple the PIC to one or more optical fibers. The PIC includes a first interface with at least two recesses and one or more grooves positioned between the recesses, and the optical coupler includes a second interface with at least two protrusions and one or more ridges positioned between the protrusions (or vice versa). The protrusions on the optical coupler are mated with the recesses on the PIC, and the ridges on the optical coupler are mated with the grooves on the PIC.