公开(公告)号：US20230289303A1

公开(公告)日：2023-09-14

申请号：US18040944

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Shijie LIU ,  Tao XU ,  Lei ZHU ,  Yufu LI

IPC: G06F13/16 ,  G06F13/10 ,  G06F13/42

CPC classification number: G06F13/1652 ,  G06F13/102 ,  G06F13/4221

Abstract: Embodiments are directed to improving remote traffic performance on cluster-aware processors. An embodiment of a system includes at least one processor package comprising a plurality of processor ports and a plurality of system agents; and a memory device to store platform initialization firmware to cause the processing system to: determine first locations of the plurality of processor ports in the at least one processor package; determine second locations of the plurality of system agents in the at least one processor package; associate each of the processor ports with a set of the plurality of system agents based on the determined first and second locations; and program the plurality of system agents with the associated processor port for the respective system agent.

公开(公告)号：US20230070411A1

公开(公告)日：2023-03-09

申请号：US17987382

申请日：2022-11-15

Applicant: Intel Corporation

Inventor： Min LIU ,  Xiang LI ,  Shijie LIU ,  Yannan SUN ,  Lei ZHU

IPC: G06F3/06 ,  G06F12/0815

Abstract: Examples described herein relate to a central processing unit (CPU) that includes at least two cores, at least two caching agents (CAs), and circuitry to monitor a workload mapped to a CA of the at least two CAs and adjust the workload allocated to the CA to allocation among the CA and at least one other CA of the at least two CAs based on the monitored workload.

公开(公告)号：US20250004878A1

公开(公告)日：2025-01-02

申请号：US18539380

申请日：2023-12-14

Applicant: Intel Corporation

Inventor： Yanxin ZHAO ,  Tao XU ,  Yufu LI ,  Shijie LIU ,  Lei ZHU

IPC: G06F11/10

Abstract: A method and system for error check and scrub (ECS) error data collection and reporting for a memory device. A controller includes circuitry and a buffer. The circuitry may be configured to read ECS error data from a register of a memory device and calculate an ECS error increase rate based on the ECS error data. The circuitry may be configured to inform basic input output system (BIOS) by interrupt if a total number of ECS errors reaches or exceeds an ECS error number threshold or if the ECS error increase rate reaches or exceeds an ECS error rate threshold. The controller may be an out-of-band device, e.g., a baseboard management controller or a memory micro controller.

公开(公告)号：US20230176735A1

公开(公告)日：2023-06-08

申请号：US17997030

申请日：2020-05-22

Applicant: INTEL CORPORATION

Inventor： Keivin Yufu LI ,  Zhenfu CHAI ,  Lei ZHU ,  Junjie HE ,  Shijie LIU ,  Tao XU

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0673 ,  G06F3/0632

Abstract: Systems, apparatuses and methods may provide for technology that initializes a host-managed device memory (HDM) as a temporary proxy for a system memory, wherein the HDM is associated with an accelerator. The technology also creates a shadow copy of boot firmware code in the HDM and executes one or more boot instructions in the shadow copy of the boot firmware code. In one example, the one or more boot instructions are to be one or more of executed before an initialization of the system memory or executed in parallel with the initialization of the system memory.

公开(公告)号：US20230041115A1

公开(公告)日：2023-02-09

申请号：US17794856

申请日：2020-02-24

Applicant: Intel Corporation

Inventor： Ping WU ,  Yingwen CHEN ,  Lei ZHU ,  Zhenglong WU ,  Tao XU

IPC: G06F9/4401 ,  G06F9/50

Abstract: Systems, apparatuses and methods may provide for technology that initializes an integrated memory of a processor during a boot sequence and conducts a runtime initialization of an external system memory associated with the processor. The technology may also bypass the runtime initialization of the external system memory during the boot sequence.