PAIRING OF BASE AND DETACHABLE DEVICE
    264.
    发明申请
    PAIRING OF BASE AND DETACHABLE DEVICE 审中-公开
    基座和可拆卸装置的配对

    公开(公告)号:US20120174199A1

    公开(公告)日:2012-07-05

    申请号:US12985182

    申请日:2011-01-05

    Abstract: An apparatus and method for pairing a base and a detachable device. A query module queries a detachable device in response to the detachable device connecting to a base. The detachable device provides a display for the base if the detachable device and base are connected. A determination module determines if the detachable device is paired with the base. A credential module obtains a pairing credential for a pairing in response to the determination module determining that the detachable device is unpaired with the base.

    Abstract translation: 一种用于配对基座和可拆卸装置的装置和方法。 响应于可拆卸设备连接到基座,查询模块查询可拆卸设备。 如果可拆卸的设备和基座已连接,则可拆卸设备为基座提供显示。 确定模块确定可拆卸设备是否与基座配对。 凭证模块响应于确定模块确定可拆卸设备与基座不配对而获得用于配对的配对凭证。

    METHOD FOR DEMODULATING DATA AND DEMODULATING APPARATUS BASED ON A DOWNLINK TRANSMIT DIVERSITY MODE IN A LTE SYSTEM
    265.
    发明申请
    METHOD FOR DEMODULATING DATA AND DEMODULATING APPARATUS BASED ON A DOWNLINK TRANSMIT DIVERSITY MODE IN A LTE SYSTEM 有权
    基于LTE系统中的下行链路发射多样性模式解调数据和解调装置的方法

    公开(公告)号:US20110292827A1

    公开(公告)日:2011-12-01

    申请号:US13148095

    申请日:2010-04-14

    Applicant: Bin Li

    Inventor: Bin Li

    CPC classification number: H04B7/0689 H04B7/0837 H04L1/0606

    Abstract: A demodulating method and a demodulating apparatus at a receiver based on a downlink transmit diversity mode in a LTE system are provided by the present invention. The method includes: dividing received data from sub-carriers of each receiving antenna based on a transmit diversity mode into multiple groups of received data according to numbers of antennas of a transmitter and a receiver; performing an independent demodulation on each group of the multiple groups of received data separately according to a demodulation algorithm of two-port transmitting and single-port receiving, so as to obtain a corresponding group of demodulated data; and for multiple groups of demodulated data corresponding to same transmitted data, performing a maximum ratio combination on the multiple groups of demodulated data according to a channel condition corresponding to each group of the multiple groups of demodulated data, so as to obtain a corresponding final demodulated data value. The demodulating method and the demodulating apparatus of the present invention can ensure the performance of the system adopting the diversity algorithm in situations of various kinds of antenna configurations, reduce cost and the complexity of devices in a practical application, and is very easy for project implementation.

    Abstract translation: 本发明提供了一种基于LTE系统中的下行链路发射分集模式的接收机的解调方法和解调装置。 该方法包括:根据发射机和接收机的天线数量,将基于发射分集模式的每个接收天线的子载波的接收数据分成多组接收数据; 根据双端口发送和单端口接收的解调算法分别对多组接收数据的每组进行独立解调,以获得相应的解调数据组; 以及对应于相同发送数据的多组解调数据,根据对应于多组解调数据的每个组的信道条件对多组解调数据执行最大比组合,以获得对应的最终解调 数据值。 本发明的解调方法和解调装置可以确保在各种天线配置情况下采用分集算法的系统的性能,在实际应用中降低设备的成本和复杂度,并且项目实现非常容易 。

    HIERARCHICALLY DISASSEMBLING MESSAGES
    266.
    发明申请
    HIERARCHICALLY DISASSEMBLING MESSAGES 有权
    高效地解散消息

    公开(公告)号:US20110264738A1

    公开(公告)日:2011-10-27

    申请号:US12767091

    申请日:2010-04-26

    CPC classification number: G06F9/545 H04L67/02 H04L69/22

    Abstract: The present invention extends to methods, systems, and computer program products for hierarchically disassembling messages. The functionality of disassemblers and framers is decoupled such that framers for different types of messages can be utilized at the same level in a hierarchy without having to also change disassemblers. Virtually any level of disassembly is possible to address any corresponding level of message nesting. Disassembly can be performed on a per message or per session basis.

    Abstract translation: 本发明扩展到用于分级拆卸消息的方法,系统和计算机程序产品。 反汇编器和成帧器的功能被解耦,使得用于不同类型的消息的成帧器可以在层次结构中的相同级别上被利用,而不必也改变反汇编器。 几乎任何级别的拆卸都可以解决任何相应级别的消息嵌套。 可以在每个消息或每个会话的基础上执行拆卸。

    System and method for self-correcting the multiphase clock
    267.
    发明申请
    System and method for self-correcting the multiphase clock 审中-公开
    用于自校正多相时钟的系统和方法

    公开(公告)号:US20110261915A1

    公开(公告)日:2011-10-27

    申请号:US13091027

    申请日:2011-04-20

    Applicant: Bin Li

    Inventor: Bin Li

    CPC classification number: G06F1/06 H03L7/0814 H03L7/091 H04L7/043

    Abstract: A system for self-correcting the multiphase clock includes a transmitter, a receiver, a random code generator and a controller. The random code generator generates a random code stream, the random code stream is transformed to the high-speed serial data by the transmitter, the high-speed serial data are sent into the receiver and transformed to the parallel data by the receiver, the parallel data are sent into the controller, the controller stores the random code stream and detects the probability of the bit error of the parallel data output by the receiver. According to the test result of the bit error, the controller generates a phase adjustment control signal for adjusting the phase uniformity of the multiphase clock. Also, a method for self-correcting the phase uniformity of the multiphase clock of the present invention effectively makes up the sampling bit errors caused by the phase nonuniformity of the multiphase clock.

    Abstract translation: 用于自校正多相时钟的系统包括发射机,接收机,随机码发生器和控制器。 随机码发生器生成随机码流,随机码流由发射机转换为高速串行数据,高速串行数据被发送到接收机,并由接收机转换成并行数据,并行 数据被发送到控制器中,控制器存储随机码流,并检测由接收机输出的并行数据的位错误的概率。 根据比特误差的测试结果,控制器产生用于调整多相时钟的相位均匀性的相位调整控制信号。 此外,用于自校正本发明的多相时钟的相位均匀性的方法有效地构成由多相时钟的相位不均匀性引起的采样位错误。

    Analog access circuit for validating chalcogenide memory cells
    269.
    发明授权
    Analog access circuit for validating chalcogenide memory cells 有权
    用于验证硫族化物记忆单元的模拟访问电路

    公开(公告)号:US07986550B2

    公开(公告)日:2011-07-26

    申请号:US12525510

    申请日:2008-11-26

    Abstract: An analog access circuit for characterizing chalcogenide memory cells is disclosed. The analog access circuit includes an analog access control module, an address and data control module, and an analog cell access and current monitoring module. The analog access control module selectively controls whether a normal memory access or an analog memory access should be performed on a specific chalcogenide memory cell. The address and data control module allows a normal memory access to the chalcogenide memory cell according to an input address. The analog cell access and current monitoring module performs an analog memory access to the chalcogenide memory cell according to the input address, and monitors a reference current from a sense amplifier associated with the chalcogenide memory cell.

    Abstract translation: 公开了一种用于表征硫族化物存储器单元的模拟存取电路。 模拟访问电路包括模拟访问控制模块,地址和数据控制模块以及模拟单元访问和电流监控模块。 模拟访问控制模块选择性地控制是否应该在特定的硫族化物存储器单元上执行正常存储器存取或模拟存储器访问。 地址和数据控制模块允许根据输入地址对硫属化物存储器单元进行正常存储器访问。 模拟电池接入和电流监测模块根据输入地址对硫族化物存储单元进行模拟存储器存取,并监测来自与硫族化物存储单元相关联的读出放大器的参考电流。

    Pen holder
    270.
    外观设计
    Pen holder 有权
    笔筒

    公开(公告)号:USD638881S1

    公开(公告)日:2011-05-31

    申请号:US29366152

    申请日:2010-07-20

    Applicant: Bin Li

    Designer: Bin Li

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