公开(公告)号：US07018895B2

公开(公告)日：2006-03-28

申请号：US11102066

申请日：2005-04-08

Applicant: Yi Ding

Inventor： Yi Ding

IPC: H01L21/336

CPC classification number: H01L27/11526 ,  G11C16/0458 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883 ,  H01L29/7885 ,  H01L29/7887

Abstract: In a memory cell (110) having multiple floating gates (160), the select gate (140) is formed before the floating gates. In some embodiments, the memory cell also has control gates (170) formed after the select gate. Substrate isolation regions (220) are formed in a semiconductor substrate (120). The substrate isolation regions protrude above the substrate. Then select gate lines (140) are formed. Then a floating gate layer (160) is deposited. The floating gate layer is etched until the substrate isolation regions are exposed. A dielectric (164) is formed over the floating gate layer, and a control gate layer (170) is deposited. The control gate layer protrudes upward over each select gate line. These the control gates and the floating gates are defined independently of photolithographic alignment. In another aspect, a nonvolatile memory cell has at least two conductive floating gates (160). A dielectric layer (164) overlying the floating gate has a continuous feature that overlies the floating gate and also overlays a sidewall of the select gate (140). Each control gate (160) overlies the continuous feature of the dielectric layer and also overlies the floating gate. In another aspect, substrate isolation regions (220) are formed in a semiconductor substrate. Select gate lines cross over the substrate isolation regions. Each select gate line has a planar top surface, but its bottom surface goes up and down over the substrate isolation regions. Other features are also provided.

Abstract translation: 在具有多个浮动栅极（160）的存储单元（110）中，在浮置栅极之前形成选择栅极（140）。 在一些实施例中，存储器单元还具有在选择栅极之后形成的控制栅极（170）。 衬底隔离区（220）形成在半导体衬底（120）中。 衬底隔离区突出于衬底上方。 然后选择栅极线（140）。 然后沉积浮栅层（160）。 蚀刻浮栅，直到衬底隔离区露出。 在浮动栅极层上形成电介质（164），并沉积控制栅极层（170）。 控制栅极层在每个选择栅极线上向上突出。 这些控制栅极和浮置栅极独立于光刻对准来定义。 在另一方面，非易失性存储单元具有至少两个导电浮动栅极（160）。 覆盖浮动栅极的介电层（164）具有覆盖在浮动栅极上并且还覆盖选择栅极（140）的侧壁的连续特征。 每个控制栅极（160）覆盖在电介质层的连续特征上并且也覆盖在浮动栅极上。 在另一方面，衬底隔离区（220）形成在半导体衬底中。 选择栅极线跨越衬底隔离区。 每个选择栅线具有平坦的顶表面，但其底表面在衬底隔离区上方上下移动。 还提供其他功能。

公开(公告)号：US07005338B2

公开(公告)日：2006-02-28

申请号：US10252143

申请日：2002-09-19

Applicant: Yi Ding ,  Vei-Han Chan

Inventor： Yi Ding ,  Vei-Han Chan

IPC: H01L29/788

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/66825

Abstract: A floating gate (110) of a nonvolatile memory cell is formed in a trench (114) in a semiconductor substrate (220). A dielectric (128) covers the surface of the trench. The wordline (140) has a portion overlying the trench. The cell's floating gate transistor has a first source/drain region (226), a channel region (224), and a second source/drain region (130). The dielectric (128) is stronger against leakage near at least a portion of the first source/drain region (122) than near at least a portion of the channel region. The stronger portion (128.1) of the additional dielectric improves data retention without increasing the programming and erase times if the programming and erase operations do not rely on a current through the stronger portion. Additional dielectric (210) has a portion located below the top surface of the substrate between the trench and a top part of the second source/drain region (130). The second source/drain region has a part located below the additional dielectric and meeting the trench. The additional dielectric can be formed with shallow trench isolation technology. The additional dielectric reduces the capacitance between the second source/drain region (130) and the floating gate.

Abstract translation: 非易失性存储单元的浮动栅极（110）形成在半导体衬底（220）中的沟槽（114）中。 电介质（128）覆盖沟槽的表面。 字线（140）具有覆盖沟槽的部分。 电池的浮栅晶体管具有第一源极/漏极区域（226），沟道区域（224）和第二源极/漏极区域（130）。 电介质（128）比在第一源极/漏极区域（122）的至少一部分附近比在沟道区域的至少一部分附近的泄漏更强。 如果编程和擦除操作不依赖于通过较强部分的电流，则附加介质的较强部分（128.1）可提高数据保持，而不会增加编程和擦除时间。 附加电介质（210）具有位于沟槽和第二源极/漏极区域（130）的顶部之间的衬底顶表面下方的部分。 第二源极/漏极区域具有位于附加电介质下方并满足沟槽的部分。 附加电介质可以用浅沟槽隔离技术形成。 附加电介质减小了第二源极/漏极区域（130）和浮动栅极之间的电容。

公开(公告)号：US07003366B1

公开(公告)日：2006-02-21

申请号：US11109225

申请日：2005-04-18

Applicant: Hung-Wen Chiou

Inventor： Hung-Wen Chiou

IPC: G06F15/18 ,  G06F19/00

CPC classification number: G06N5/048 ,  G06N5/045

Abstract: An operating method for a fault detection of a semiconductor process and a diagnostic system for fault detection in a semiconductor process are described. By using the method and the diagnostic system, the real-time process parameters collected during the process is performed by the tool become meaningful and are correlated with the historic process performance data obtained by the post process metrology process. Moreover, the method and the diagnostic system further provide an alarm index for the process performed on the tool to actually reflect the process environment during the process is performed after correlating the real-time process parameters and the historic process performance data. With referring to the alarm index, the current process performance under the real-time process parameters in the tool can be accurately diagnosed.

Abstract translation: 描述了用于半导体工艺的故障检测的操作方法和用于半导体工艺中的故障检测的诊断系统。 通过使用该方法和诊断系统，该过程中收集的实时过程参数由工具执行变得有意义，并与后处理计量过程获得的历史过程绩效数据相关。 此外，该方法和诊断系统进一步提供了在工具上执行的过程的报警指标，以便在将实时过程参数和历史过程执行数据相关联之后，在处理过程中实际反映过程环境。 通过参考报警指标，可以准确地诊断工具中实时过程参数下的当前进程性能。

公开(公告)号：US20060033147A1

公开(公告)日：2006-02-16

申请号：US10981653

申请日：2004-11-05

Applicant: Ming Tang

Inventor： Ming Tang

IPC: H01L21/336 ,  H01L29/76

CPC classification number: H01L29/66825 ,  H01L27/115 ,  H01L27/11553 ,  H01L29/40114 ,  H01L29/7885

Abstract: A flash memory structure comprises a semiconductor substrate, a source region, a drain region, a first insulating dielectric layer, a floating gate, a second insulating dielectric layer, and a control gate. The semiconductor substrate has a first top surface and a second top surface that is lower than the first top surface. The source region and the drain region are respectively in the second top surface and the first top surface of the semiconductor substrate, and the semiconductor substrate connecting the source region and the drain region is a vertical channel region. The whole channel region is covered by the first insulating dielectric layer, the floating gate, the second insulating dielectric layer, and the control gate in turn.

Abstract translation: 闪存结构包括半导体衬底，源极区，漏极区，第一绝缘介电层，浮栅，第二绝缘介质层和控制栅。 半导体衬底具有比第一顶表面低的第一顶表面和第二顶表面。 源极区域和漏极区域分别位于半导体衬底的第二顶表面和第一顶表面中，并且连接源极区域和漏极区域的半导体衬底是垂直沟道区域。 整个通道区域依次由第一绝缘介电层，浮置栅极，第二绝缘介电层和控制栅极覆盖。

公开(公告)号：US06962851B2

公开(公告)日：2005-11-08

申请号：US10393212

申请日：2003-03-19

Applicant: Yi Ding

Inventor： Yi Ding

IPC: H01L27/092 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11526 ,  H01L27/115 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/66825

Abstract: In a nonvolatile memory, substrate isolation regions (220) are formed in a semiconductor substrate (120). The substrate isolation regions are dielectric regions protruding above the substrate. Then select gate lines (140) are formed. Then a floating gate layer (160) is deposited. The floating gate layer is etched until the substrate isolation regions are exposed and the floating layer is removed from over at least a portion of the select gate lines. A dielectric (1510) is formed over the floating gate layer, and a control gate layer (170) is deposited. The control gate layer protrudes upward over each select gate line. These protrusions are exploited to define the control gates independently of photolithographic alignment. The floating gates are then defined independently of any photolithographic alignment other than the alignment involved in patterning the substrate isolation regions and the select gate lines. In another aspect, a nonvolatile memory cell has a conductive floating gate (160). A dielectric layer (1510) overlying the floating gate has a continuous feature that overlies the floating gate and also overlies the select gate (140). The control gate (160) overlies the continuous feature of the dielectric layer and also overlies the floating gate but not the select gate. In another aspect, substrate isolation regions (220) are formed in a semiconductor substrate. Select gate lines cross over the substrate isolation regions. Each select gate line has a planar top surface, but its bottom surface goes up and down over the substrate isolation regions. Other features are also provided.

Abstract translation: 在非易失性存储器中，在半导体衬底（120）中形成衬底隔离区（220）。 衬底隔离区域是突出于衬底上方的电介质区域。 然后选择栅极线（140）。 然后沉积浮栅层（160）。 蚀刻浮栅，直到衬底隔离区被暴露，并且浮选层从至少一部分选择栅极线上去除。 在浮动栅极层上形成电介质（1510），并沉积控制栅极层（170）。 控制栅极层在每个选择栅极线上向上突出。 这些突起被利用来独立于光刻对准来限定控制栅。 然后，浮动栅极独立于除图案化衬底隔离区域和选择栅极线之外的对准的任何光刻对准。 在另一方面，非易失性存储单元具有导电浮动栅极（160）。 覆盖浮置栅极的介电层（1510）具有覆盖在浮动栅极上并且还覆盖选择栅极（140）的连续特征。 控制栅极（160）覆盖在电介质层的连续特征上，并且覆盖在浮动栅极而不是选择栅极。 在另一方面，衬底隔离区（220）形成在半导体衬底中。 选择栅极线跨越衬底隔离区。 每个选择栅线具有平坦的顶表面，但其底表面在衬底隔离区上方上下移动。 还提供其他功能。

公开(公告)号：US06951782B2

公开(公告)日：2005-10-04

申请号：US10632186

申请日：2003-07-30

Applicant: Yi Ding

Inventor： Yi Ding

IPC: G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L21/332

CPC classification number: H01L27/11526 ,  G11C16/0458 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/7887

Abstract: In a nonvolatile memory cell having at least two floating gates, each floating gate (160) has an upward protruding portion. This portion can be formed as a spacer over a sidewall of the select gate (140). The spacer can be formed from a layer (160.2) deposited after the layer (160.1) which provides a lower portion of the floating gate. Alternatively, the upward protruding portion and the lower portion can be formed from the same layers or sub-layers all of which are present in both portions. The control gate (170) can be defined without photolithography. Other embodiments are also provided.

Abstract translation: 在具有至少两个浮动栅极的非易失性存储单元中，每个浮动栅极（160）具有向上突出部分。 该部分可以形成为在选择门（140）的侧壁上的间隔物。 隔离物可以由沉积在提供浮动栅极的下部的层（160.1）之后的层（160.2）形成。 或者，向上突出部分和下部分可以由相同的层或子层形成，所有这些层或子层都存在于两个部分中。 控制栅极（170）可以在没有光刻的情况下被定义。 还提供了其他实施例。

公开(公告)号：US06947806B2

公开(公告)日：2005-09-20

申请号：US10655850

申请日：2003-09-04

Applicant: Wun Wang

Inventor： Wun Wang

IPC: G05B23/02 ,  G06F19/00

CPC classification number: G05B23/0221

Abstract: This invention relates to a method for yield loss analysis of process steps of semiconductor wafers having a plurality of dies, and more particularly relates to a defect inspection technique to determine a hit ratio, computation of yield impact contributions for the defects, and determination of a kill ratio for a specific type of defect. Yield loss is estimated ultimately upon a choice of a defect density distribution function. A defect calibrated factor and a yield impact calibrated factor are introduced herein.

Abstract translation: 本发明涉及一种具有多个模具的半导体晶片的工艺步骤的屈服损耗分析方法，更具体地说，涉及一种用于确定命中率的缺陷检查技术，缺陷的屈服应力贡献的计算和 杀死比例为特定类型的缺陷。 最终在选择缺陷密度分布函数时估计产量损失。 本文介绍了缺陷校准因子和屈服冲击校准因子。

公开(公告)号：US06943098B2

公开(公告)日：2005-09-13

申请号：US10605326

申请日：2003-09-23

Applicant: Fang-Yu Yeh ,  Chun-Che Chen

Inventor： Fang-Yu Yeh ,  Chun-Che Chen

IPC: H01L21/31 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/469 ,  H01L21/4763 ,  H01L21/477 ,  H01L21/60 ,  H01L21/768

CPC classification number: H01L21/76897 ,  H01L21/76838 ,  H01L29/6656

Abstract: A method of forming a contact opening is provided. First, a substrate having a plurality of conductive structures formed thereon is provided. An ion implantation is performed. Thereafter, a thermal treatment is carried out to form a liner layer on the sidewall of the conductive structure and the exposed substrate. The liner layer on the sidewall of the conductive structure has a thickness smaller than the liner layer on the substrate surface. A spacer is formed on each side of the conductive structure and then an insulation layer is formed over the substrate. The insulation layer is patterned to form a contact opening between two neighboring conductive structures. Since the liner layer on the sidewall of the conductive structures is already quite thin, there is no need to reduce thickness through an etching operation and uniformity of the liner layer on the substrate can be ensured.

Abstract translation: 提供一种形成接触开口的方法。 首先，提供其上形成有多个导电结构的基板。 进行离子注入。 此后，进行热处理以在导电结构的侧壁和暴露的基板上形成衬垫层。 导电结构的侧壁上的衬垫层的厚度小于衬底表面上的衬垫层。 在导电结构的每一侧上形成间隔物，然后在衬底上形成绝缘层。 图案化绝缘层以在两个相邻导电结构之间形成接触开口。 由于导电结构的侧壁上的衬垫层已经相当薄，所以不需要通过蚀刻操作来减小厚度，并且可以确保衬底上的衬垫层的均匀性。

公开(公告)号：US06903592B2

公开(公告)日：2005-06-07

申请号：US10349281

申请日：2003-01-22

Applicant: Jon Allan Faue

Inventor： Jon Allan Faue

IPC: G06F1/04 ,  H03K5/156 ,  H03K3/00

CPC classification number: H03K5/1565 ,  G06F1/04

Abstract: A circuit and method of generating an internal chip clock signal for distribution throughout an integrated circuit in response to an external clock signal includes the steps of generating a minimum width internal clock signal if the width of the external clock signal is less than a predetermined minimum width, generating an internal clock signal having a width substantially equal to the width of the external clock signal if the width of the external clock signal is greater than a predetermined minimum width but less than a predetermined maximum width, and generating a maximum width internal clock signal if the width of the external clock signal is greater than a predetermined maximum width.

Abstract translation: 一种用于响应外部时钟信号产生用于分布在整个集成电路中的内部芯片时钟信号的电路和方法包括以下步骤：如果外部时钟信号的宽度小于预定的最小宽度，则产生最小宽度的内部时钟信号 如果所述外部时钟信号的宽度大于预定的最小宽度但小于预定的最大宽度，则产生具有基本上等于所述外部时钟信号的宽度的宽度的内部时钟信号，以及产生最大宽度的内部时钟信号 如果外部时钟信号的宽度大于预定的最大宽度。

公开(公告)号：US06902974B2

公开(公告)日：2005-06-07

申请号：US10440466

申请日：2003-05-16

Applicant: Yi Ding

Inventor： Yi Ding

IPC: H01L21/3205 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/105

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11546

Abstract: A control gate layer (170) for a nonvolatile memory cell is formed over a select gate (140). The control gate layer protrudes upward over the select gate. An auxiliary layer (1710) is formed over the control gate layer so as to expose a protruding portion of the control gate layer. The protruding portion is processed (e.g. oxidized) to form a protective layer (1720) selectively on the control gate layer but not on the auxiliary layer. The auxiliary layer is then removed. Then the control gate layer is etched selectively to the protective layer. The protruding portion of the control gate layer is not etched away because it is protected by the protective layer. This portion provides a self-aligned control gate. The protective layer can then be removed, and a conductive material (2920), e.g. metal silicide, can be formed selectively on the protruding portion of the control gate layer in a self-aligned manner to reduce the control gate resistance. Other embodiments are also provided.

Abstract translation: 用于非易失性存储单元的控制栅极层（170）形成在选择栅极（140）上。 控制栅极层在选择栅极上向上突出。 辅助层（1710）形成在控制栅极层上，以暴露控制栅极层的突出部分。 突出部分被处理（例如氧化）以在控制栅极层上选择性地形成保护层（1720），但不在辅助层上。 然后除去辅助层。 然后将控制栅层选择性地蚀刻到保护层。 控制栅极层的突出部分不被蚀刻掉，因为它被保护层保护。 该部分提供自对准控制门。 然后可以去除保护层，并且导电材料（2920） 金属硅化物可以以自对准方式选择性地形成在控制栅极层的突出部分上，以减小控制栅极电阻。 还提供了其他实施例。