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公开(公告)号:US11145725B2
公开(公告)日:2021-10-12
申请号:US16823005
申请日:2020-03-18
Applicant: GLOBALFOUNDRIES U.S. INC.
Inventor: Qizhi Liu , Vibhor Jain , Judson R. Holt , Herbert Ho , Claude Ortolland , John J. Pekarik
IPC: H01L29/417 , H01L29/66 , H01L29/737 , H01L29/08
Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor and methods of manufacture. The structure includes: a sub-collector region; a collector region in electrical connection to the sub-collector region; an emitter located adjacent to the collector region and comprising emitter material, recessed sidewalls on the emitter material and an extension region extending at an upper portion of the emitter material above the recessed sidewalls; and an extrinsic base separated from the emitter by the recessed sidewalls.
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公开(公告)号:US11145606B1
公开(公告)日:2021-10-12
申请号:US16830543
申请日:2020-03-26
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: Nicholas A. Polomoff , Jae Kyu Cho , Mohamed A. Rabie , Andreas D. Stricker
IPC: H01L23/00 , H01L23/522 , H01L31/02 , H01L33/62
Abstract: Structures for an optical fiber groove and methods of forming a structure for an optical fiber groove. A photonics chip includes a substrate and an interconnect structure over the substrate. The photonics chip has a first exterior corner, a second exterior corner, and a side edge extending from the first exterior corner to the second exterior corner. The substrate includes a groove positioned along the side edge between the first exterior corner and the second exterior corner. The groove is arranged to intersect the side edge at a groove corner, and the interconnect structure includes metal structures adjacent to the first groove corner. The metal structures extend diagonally in the interconnect structure relative to the side edge of the photonics chip.
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公开(公告)号:US20210311253A1
公开(公告)日:2021-10-07
申请号:US16837149
申请日:2020-04-01
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: Yusheng Bian , Bo Peng
Abstract: Structures for an optical coupler and methods of fabricating a structure for an optical coupler. A coupling section has a plurality of segments arranged with a pitch, a first waveguide core has a section extending longitudinally over the first plurality of segments of the coupling section, and a second waveguide core has a section extending longitudinally over the coupling section. The section of the second waveguide core laterally spaced from the section of the first waveguide core by a given distance.
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公开(公告)号:US20210305251A1
公开(公告)日:2021-09-30
申请号:US16832139
申请日:2020-03-27
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: Dali Shao , Tao Chu , Liqiao Qin
IPC: H01L27/092 , H01L29/49 , H01L21/8238 , H01L21/28
Abstract: One illustrative IC product disclosed herein includes a semiconductor substrate and a first transistor device formed on the semiconductor substrate. The first transistor device comprises a first gate structure. The first gate structure comprises a gate insulation layer, a first layer of titanium nitride (TiN) positioned above the gate insulation layer, a layer of titanium silicon nitride (TiSiN) positioned above the first layer of TiN and a second layer of titanium nitride (TiN) positioned above the layer of TiSiN.
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公开(公告)号:US11127674B2
公开(公告)日:2021-09-21
申请号:US16654059
申请日:2019-10-16
Applicant: GLOBALFOUNDRIES U.S. INC.
Inventor: Dirk Breuer , Oliver M. Witnik , Carla Byloos , Holger S. Schuehrer
IPC: H01L23/522 , H01L23/532 , H01L21/768 , H01L23/528
Abstract: Disclosed are embodiments of a back end of the line (BEOL) metal structure that includes, within a metal level, a metal via, which has at least eight sides and all interior angles at 135° or more, and a metal wire thereon. The metal wire and via include respective portions of a continuous conformal metal layer. A passivation layer coats the top surface of the metal layer. The metal via and the metal wire thereon can be in an upper metal level and can be made of one metal (e.g., aluminum or an aluminum alloy). The upper metal level can be above a lower metal level that similarly includes a metal via and metal wire thereon, but the metal used can be different (e.g., copper) and/or the shape of the via can be different (e.g., four-sided). Also disclosed herein are method embodiments for forming the above-described BEOL metal structure.
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公开(公告)号:US11127623B2
公开(公告)日:2021-09-21
申请号:US16213189
申请日:2018-12-07
Applicant: GLOBALFOUNDRIES U.S. INC.
Inventor: Hui Zang , Ruilong Xie , Jessica M. Dechene
IPC: H01L21/308 , H01L21/762 , H01L29/66 , H01L27/088
Abstract: The present disclosure relates to semiconductor structures and, more particularly, to single diffusion cut for gate structures and methods of manufacture. The structure includes a single diffusion break extending into a substrate between diffusion regions of adjacent gate structures, the single diffusion break filled with an insulator material and further comprising an undercut region lined with a liner material which is between the insulator material and the diffusion regions.
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公开(公告)号:US11121097B1
公开(公告)日:2021-09-14
申请号:US16881736
申请日:2020-05-22
Applicant: GLOBALFOUNDRIES U.S. INC.
Inventor: Vibhor Jain , Sebastian T. Ventrone , Siva P. Adusumilli , John J. Ellis-Monaghan , Ajay Raman
Abstract: The present disclosure relates to a metal layer for an active x-ray attack prevention device for securing integrated circuits. In particular, the present disclosure relates to a structure including a semiconductor material, one or more devices on a front side of the semiconductor material, a backside patterned metal layer under the one or more devices, located and structured to protect the one or more devices from an active intrusion, and at least one contact providing an electrical connection through the semiconductor material to a front side of the backside patterned metal layer. The backside patterned metal layer is between a wafer and one of the semiconductor material and an insulator layer.
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公开(公告)号:US20210280699A1
公开(公告)日:2021-09-09
申请号:US16810076
申请日:2020-03-05
Applicant: GLOBALFOUNDRIES U.S. INC.
Inventor: Anindya NATH , Alain F. LOISEAU
Abstract: The present disclosure relates to a polysilicon-diode triggered compact silicon controlled rectifier. In particular, the present disclosure relates to a structure including a silicon controlled rectifier (SCR) which includes an n-well adjacent and in direct contact with a p-well, the SCR includes at least one shallow trench isolation (STI) region, and at least one polysilicon diode on top of the at least one STI region.
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279.
公开(公告)号:US11114466B2
公开(公告)日:2021-09-07
申请号:US16774087
申请日:2020-01-28
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: Sipeng Gu , Jiehui Shu , Haiting Wang
IPC: H01L27/12 , H01L21/762 , H01L21/306 , H01L21/84 , H01L21/265 , H01L21/76
Abstract: One illustrative IC product disclosed herein includes an (SOI) substrate comprising a base semiconductor layer, a buried insulation layer and an active semiconductor layer positioned above the buried insulation layer. In this particular example, the IC product also includes a first region of localized high resistivity formed in the base semiconductor layer, wherein the first region of localized high resistivity has an electrical resistivity that is greater than an electrical resistivity of the material of the base semiconductor layer. The IC product also includes a first region comprising integrated circuits formed above the active semiconductor layer, wherein the first region comprising integrated circuits is positioned vertically above the first region of localized high resistivity in the base semiconductor layer.
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公开(公告)号:US20210273061A1
公开(公告)日:2021-09-02
申请号:US16803711
申请日:2020-02-27
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: Haiting Wang , Tamilmani Ethirajan , Zhenyu Hu , Tung-Hsing Lee
IPC: H01L29/417 , H01L29/08 , H01L29/10 , H01L29/423 , H01L29/73
Abstract: One illustrative device disclosed herein includes a semiconductor substrate and a bipolar junction transistor (BJT) device that comprises a collector region, a base region and an emitter region. In this example, the device also includes a field effect transistor and at least one base conductive contact structure that conductively and physically contacts the base region.
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