Corner structures for an optical fiber groove

    公开(公告)号:US11145606B1

    公开(公告)日:2021-10-12

    申请号:US16830543

    申请日:2020-03-26

    Abstract: Structures for an optical fiber groove and methods of forming a structure for an optical fiber groove. A photonics chip includes a substrate and an interconnect structure over the substrate. The photonics chip has a first exterior corner, a second exterior corner, and a side edge extending from the first exterior corner to the second exterior corner. The substrate includes a groove positioned along the side edge between the first exterior corner and the second exterior corner. The groove is arranged to intersect the side edge at a groove corner, and the interconnect structure includes metal structures adjacent to the first groove corner. The metal structures extend diagonally in the interconnect structure relative to the side edge of the photonics chip.

    OPTICAL COUPLERS WITH SEGMENTED WAVEGUIDES

    公开(公告)号:US20210311253A1

    公开(公告)日:2021-10-07

    申请号:US16837149

    申请日:2020-04-01

    Abstract: Structures for an optical coupler and methods of fabricating a structure for an optical coupler. A coupling section has a plurality of segments arranged with a pitch, a first waveguide core has a section extending longitudinally over the first plurality of segments of the coupling section, and a second waveguide core has a section extending longitudinally over the coupling section. The section of the second waveguide core laterally spaced from the section of the first waveguide core by a given distance.

    Back end of the line metal structure and method

    公开(公告)号:US11127674B2

    公开(公告)日:2021-09-21

    申请号:US16654059

    申请日:2019-10-16

    Abstract: Disclosed are embodiments of a back end of the line (BEOL) metal structure that includes, within a metal level, a metal via, which has at least eight sides and all interior angles at 135° or more, and a metal wire thereon. The metal wire and via include respective portions of a continuous conformal metal layer. A passivation layer coats the top surface of the metal layer. The metal via and the metal wire thereon can be in an upper metal level and can be made of one metal (e.g., aluminum or an aluminum alloy). The upper metal level can be above a lower metal level that similarly includes a metal via and metal wire thereon, but the metal used can be different (e.g., copper) and/or the shape of the via can be different (e.g., four-sided). Also disclosed herein are method embodiments for forming the above-described BEOL metal structure.

    Single diffusion cut for gate structures

    公开(公告)号:US11127623B2

    公开(公告)日:2021-09-21

    申请号:US16213189

    申请日:2018-12-07

    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to single diffusion cut for gate structures and methods of manufacture. The structure includes a single diffusion break extending into a substrate between diffusion regions of adjacent gate structures, the single diffusion break filled with an insulator material and further comprising an undercut region lined with a liner material which is between the insulator material and the diffusion regions.

    Active x-ray attack prevention device

    公开(公告)号:US11121097B1

    公开(公告)日:2021-09-14

    申请号:US16881736

    申请日:2020-05-22

    Abstract: The present disclosure relates to a metal layer for an active x-ray attack prevention device for securing integrated circuits. In particular, the present disclosure relates to a structure including a semiconductor material, one or more devices on a front side of the semiconductor material, a backside patterned metal layer under the one or more devices, located and structured to protect the one or more devices from an active intrusion, and at least one contact providing an electrical connection through the semiconductor material to a front side of the backside patterned metal layer. The backside patterned metal layer is between a wafer and one of the semiconductor material and an insulator layer.

    DIODE TRIGGERED COMPACT SILICON CONTROLLED RECTIFIER

    公开(公告)号:US20210280699A1

    公开(公告)日:2021-09-09

    申请号:US16810076

    申请日:2020-03-05

    Abstract: The present disclosure relates to a polysilicon-diode triggered compact silicon controlled rectifier. In particular, the present disclosure relates to a structure including a silicon controlled rectifier (SCR) which includes an n-well adjacent and in direct contact with a p-well, the SCR includes at least one shallow trench isolation (STI) region, and at least one polysilicon diode on top of the at least one STI region.

    IC products formed on a substrate having localized regions of high resistivity and methods of making such IC products

    公开(公告)号:US11114466B2

    公开(公告)日:2021-09-07

    申请号:US16774087

    申请日:2020-01-28

    Abstract: One illustrative IC product disclosed herein includes an (SOI) substrate comprising a base semiconductor layer, a buried insulation layer and an active semiconductor layer positioned above the buried insulation layer. In this particular example, the IC product also includes a first region of localized high resistivity formed in the base semiconductor layer, wherein the first region of localized high resistivity has an electrical resistivity that is greater than an electrical resistivity of the material of the base semiconductor layer. The IC product also includes a first region comprising integrated circuits formed above the active semiconductor layer, wherein the first region comprising integrated circuits is positioned vertically above the first region of localized high resistivity in the base semiconductor layer.

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