公开(公告)号：US11152807B2

公开(公告)日：2021-10-19

申请号：US16558922

申请日：2019-09-03

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Jean Camiolo ,  Christophe Lorin

IPC: H02J7/00 ,  G06F1/26 ,  H01R13/66 ,  H01R24/62 ,  G06F1/28 ,  G06F13/42 ,  H01R107/00

Abstract: A method selects one or a plurality of sets of values characterizing an electric power of a power source capable of powering a device coupled to the power source via a connection interface. The selection is carried out according to values, characterizing the power supplied by the power source, measured at the connection interface.

公开(公告)号：US20210320473A1

公开(公告)日：2021-10-14

申请号：US17223649

申请日：2021-04-06

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Fabien QUERCIA ,  Jean-Michel RIVIERE

IPC: H01S5/02234 ,  H01L31/0203 ,  H01L31/0232 ,  H01S5/00 ,  H01S5/40 ,  H01S5/0236 ,  G01S7/481

Abstract: An electronic device includes a base substrate having a mounting face. An electronic chip is fastened onto the mounting face of the base substrate. A transparent encapsulation structure is bonded onto the base substrate. The transparent encapsulation structure includes a housing with an internal cavity defining a chamber housing the electronic chip. The encapsulation structure has an external face that supports a light-filtering optical wafer located facing an optical element of the electronic chip. An opaque cover covers the transparent encapsulation structure and includes a local opening facing the light-filtering optical wafer.

公开(公告)号：US11138036B2

公开(公告)日：2021-10-05

申请号：US16739388

申请日：2020-01-10

Applicant: STMicroelectronics SA ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Bruno Denis ,  Christophe Taba

IPC: G06F9/48 ,  G06F9/54 ,  G06F12/1081 ,  G06F13/364 ,  G06F13/16 ,  G06F13/30 ,  G06F13/40

Abstract: Requests are received by a routing circuit. A plurality of first round-robin arbitration circuits are coupled to the routing circuit. There are as many first round-robin arbitration circuits as there are possible priority levels for the requests. The routing circuit operates to transmit each received request to a number of first round-robin arbitration circuits determined according to the priority level of the request. A second round-robin arbitration circuit has inputs respectively connected to the outputs of the first round-robin arbitration circuits.

公开(公告)号：US11114312B2

公开(公告)日：2021-09-07

申请号：US16394925

申请日：2019-04-25

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Benoit Besancon ,  Alexandre Mas ,  Karine Saxod

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/552 ,  H01L23/053 ,  H01L23/06 ,  H01L23/10 ,  H01L23/24 ,  H01L23/42 ,  H01L23/433 ,  H01L21/52 ,  H01L23/04 ,  H01L21/48

Abstract: A method for manufacturing a cover for an electronic package includes placing an insert having opposite faces between opposite faces of a cavity of a mold. A coating material is injected in the mold cavity around the insert. The coating material is then set to form a substrate that is overmolded around the insert and produce the cover.

公开(公告)号：US11106582B2

公开(公告)日：2021-08-31

申请号：US16530049

申请日：2019-08-02

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Gerald Briat

IPC: G06F12/0806

Abstract: A device includes first and second buffers fillable with contents of memory locations. A selection circuit is configured to select a filling mode between simultaneous filling of the buffers and sequential filling of the buffers. In some examples, the device can be a system on a chip that includes a non-volatile memory and a processor.

公开(公告)号：US11101188B2

公开(公告)日：2021-08-24

申请号：US16551241

申请日：2019-08-26

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Olivier Franiatte ,  Richard Rembert

IPC: H01L23/04 ,  H01L23/498 ,  H01L21/56 ,  H01L23/538 ,  H01L21/60 ,  H01L21/603

Abstract: A cover for an integrated circuit package includes a central plate and a peripheral frame surrounding the central plate. The peripheral frame is vertically spaced from and parallel to the central plate. The peripheral frame includes through openings formed therein. The cover can be used to package a semiconductor chip that is mounted to a substrate.

公开(公告)号：US20210240863A1

公开(公告)日：2021-08-05

申请号：US17161544

申请日：2021-01-28

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Alps) SAS

Inventor： Gilles PELISSIER ,  Nicolas ANQUET ,  Delphine LE-GOASCOZ

IPC: G06F21/72 ,  H04L9/08 ,  H04L9/06

Abstract: A unique hardware key is recorded a secure hardware environment. A first logic circuit of the secure hardware environment is configured to generate a unique derived key from said unique hardware key and at least one piece of information. The at least one piece of information relates to one or more of an execution context and a use of a secret key. The secure hardware environment further includes a first encryption device that performs a symmetric encryption of the secret key using the unique derived key. This symmetric encryption generates an encrypted secret key for use outside of the secure hardware environment.

公开(公告)号：US20210202781A1

公开(公告)日：2021-07-01

申请号：US17199180

申请日：2021-03-11

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS

Inventor： Alexandre COULLOMB ,  Romain COFFY ,  Jean-Michel RIVIERE

IPC: H01L31/16

Abstract: A device includes a substrate and an optoelectronic chip buried in the substrate. The substrate may include an opening above a first optical transduction region of the first optoelectronic chip and above a second optical transduction region of a second optoelectronic chip.

公开(公告)号：US20210173568A1

公开(公告)日：2021-06-10

申请号：US17111778

申请日：2020-12-04

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Gerald BRIAT ,  Stephane MARMEY

IPC: G06F3/06

Abstract: The integrity of a memory is checked by: storing data representative of an operation to be executed in the memory; executing the operation; and erasing the data once the execution is complete.

公开(公告)号：US11029200B2

公开(公告)日：2021-06-08

申请号：US15890533

申请日：2018-02-07

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Pascal Mellot

IPC: G01J1/42 ,  G01J1/18 ,  G01J1/44 ,  H04N1/00

Abstract: The following steps are performed in connection with a photodiode circuit: a) resetting the photodiode circuit; b) determining when a photodiode voltage changes in response to illumination to reach a threshold; and c) updating a counter in response to the determination in step b). The steps a) to c) are repeated until an end of a measurement period is reached. The value of the counter at the end of the measurement period is then output to indicate an intensity of the illumination.