公开(公告)号：US20120195094A1

公开(公告)日：2012-08-02

申请号：US13362434

申请日：2012-01-31

Applicant: MAURIZIO GRECO ,  Antonio Maria Scalia

Inventor： MAURIZIO GRECO ,  Antonio Maria Scalia

IPC: G11C11/22

CPC classification number: G11C11/22

Abstract: Logic data is written in a memory having a first word line and a first bit line, with the memory including a first memory cell having a first ferroelectric transistor. The first ferroelectric transistor includes a layer of ferroelectric material and has a first conduction terminal coupled to the first bit line, and a control terminal coupled to the first word line. The logic data is written based on biasing the control terminal of the first ferroelectric transistor at a first biasing value, biasing the first conduction terminal of the first ferroelectric transistor at a second biasing value different from the first biasing value, and generating a stable variation of the state of polarization of the layer of ferroelectric material of the first ferroelectric transistor to write the logic data in the first memory cell.

Abstract translation: 逻辑数据被写入具有第一字线和第一位线的存储器中，存储器包括具有第一铁电晶体管的第一存储单元。 第一铁电晶体管包括铁电材料层，并且具有耦合到第一位线的第一导电端子和耦合到第一字线的控制端子。 写入逻辑数据是基于将第一铁电晶体管的控制端子以第一偏置值偏置的方式写入的，将第一铁电晶体管的第一导通端子偏置在与第一偏置值不同的第二偏置值的情况下，产生稳定的变化 第一铁电晶体管的铁电材料层的极化状态将逻辑数据写入第一存储单元。

公开(公告)号：US20120169408A1

公开(公告)日：2012-07-05

申请号：US13340118

申请日：2011-12-29

Applicant: Fabio Enrico Carlo DISEGNI ,  Marco SPAMPINATO

Inventor： Fabio Enrico Carlo DISEGNI ,  Marco SPAMPINATO

IPC: G05F3/02

CPC classification number: H02M3/073 ,  H02M2003/075

Abstract: A voltage booster device may include a plurality of multiplication stages arranged in a sequence so that an input terminal of each multiplication stage, with the exception of a first multiplication stage, is connected to an output terminal of a previous multiplication stage. Each multiplication stage may include pumping circuitry for accumulating an electric charge proportional to a pump voltage value of the multiplication stage. Each multiplication stage may also include a phase signal generating circuit for switching the multiplication stages between a transfer phase and a maintaining phase. In at least one of the stages, the pumping circuitry may include at least two series connected charge accumulators. A terminal may be shared between the charge accumulators and may be connected through biasing circuitry to an output terminal of a previous multiplication stage for forcing the charge accumulators within a threshold potential drop value.

Abstract translation: 升压装置可以包括按照顺序排列的多个乘法级，使得除了第一乘法级之外的每个乘法级的输入端子连接到先前乘法级的输出端子。 每个乘法级可以包括用于累积与乘法级的泵电压值成比例的电荷的泵浦电路。 每个乘法级还可以包括用于在转换阶段和维持阶段之间切换乘法级的相位信号发生电路。 在至少一个级中，泵送电路可以包括至少两个串联连接的电荷累加器。 终端可以在电荷累加器之间共享，并且可以通过偏置电路连接到先前乘法级的输出端，以将电荷累加器强制在阈值电位下降值内。

公开(公告)号：US20120075133A1

公开(公告)日：2012-03-29

申请号：US13240227

申请日：2011-09-22

Applicant: Jesus Alejandro GUINEA TRIGO ,  Andrea Baschirotto

Inventor： Jesus Alejandro GUINEA TRIGO ,  Andrea Baschirotto

IPC: H03M3/00 ,  H05K13/00

CPC classification number: H03M3/436 ,  H03M3/45 ,  Y10T29/49002

Abstract: A sigma-delta converter may include an input node, a switched capacitor input stage integrating a difference signal between an input signal from the input node and a feedback signal representing an output signal, and a switched capacitor adder coupled downstream from the switched capacitor input stage and generating a sum signal based upon the input signal with a signal generated by the switched capacitor input stage. The sigma-delta converter may include a switched capacitor output stage amplifying the sum signal and generating an analog amplified signal, a quantization stage coupled in cascade to the switched capacitor output stage and generating the output signal as a digital replica of the analog amplified signal, and a circuit generating the feedback signal as an analog replica of the output signal.

Abstract translation: Σ-Δ转换器可以包括输入节点，将来自输入节点的输入信号与代表输出信号的反馈信号之间的差分信号进行积分的开关电容器输入级和耦合到开关电容器输入级下游的开关电容器加法器 以及基于所述输入信号产生由所述开关电容器输入级产生的信号的和信号。 Σ-Δ转换器可以包括开关电容器输出级，放大和信号并产生模拟放大信号，量化级级联耦合到开关电容器输出级并产生输出信号作为模拟放大信号的数字复制品， 以及产生反馈信号作为输出信号的模拟副本的电路。

公开(公告)号：US20120068050A1

公开(公告)日：2012-03-22

申请号：US13233172

申请日：2011-09-15

Applicant: Massimo Cataldo MAZZILLO ,  Delfo Nunziato Sanfilippo ,  Giovanni Condorelli

Inventor： Massimo Cataldo MAZZILLO ,  Delfo Nunziato Sanfilippo ,  Giovanni Condorelli

IPC: H01L27/146 ,  H01L31/0224

CPC classification number: G01J1/46 ,  H01L27/14658 ,  H01L31/107

Abstract: A multi-pixel photodetector array may include a semiconductor substrate having a back side and a front side, Geiger mode avalanche photodiodes (GM-APDs) on the semiconductor substrate, each including an anode contact, and a common cathode for the GM-APDs and having a first connection lead on the backside of the semiconductor substrate. The multi-pixel photodetector array may include a second connection lead, and a common anode on the front side of the semiconductor substrate and configured to couple in common the anode contacts of the GM-APDs to the second connection lead. Each GM-APD may be configured to generate, when a photon impinges thereon, a current pulse of different shape for discrimination by an external circuit connected to the common cathode and the common anode.

Abstract translation: 多像素光检测器阵列可以包括具有背侧和前侧的半导体衬底，半导体衬底上的Geiger模式雪崩光电二极管（GM-APD），每个包括阳极接触和用于GM-APD的公共阴极， 在半导体衬底的背面具有第一连接引线。 多像素光电检测器阵列可以包括第二连接引线和在半导体衬底的前侧上的公共阳极，并且被配置为将GM-APD的阳极触点共同地耦合到第二连接引线。 每个GM-APD可以被配置为当光子入射到其上时，产生不同形状的电流脉冲，用于由连接到公共阴极和公共阳极的外部电路进行鉴别。

公开(公告)号：US20120020400A1

公开(公告)日：2012-01-26

申请号：US13189769

申请日：2011-07-25

Applicant: Angelo POLONI ,  Stefano Valle ,  Stefano Vincenti

Inventor： Angelo POLONI ,  Stefano Valle ,  Stefano Vincenti

IPC: H04B3/46

CPC classification number: H04L1/0045 ,  H03M13/255

Abstract: A method for identifying a corrupted received signal at a receiver is described. A received signal may include symbols. Each symbol may have a value of a Galois field associated therewith. The receiver may be configured to store a logarithm of normalized probability mass functions and corresponding Galois field values for each of the plurality of symbols. The normalized probability mass functions may be normalized with respect to a greatest probability mass function of a given symbol of the plurality of symbols. The method may include comparing, for each of the plurality of symbols, a logarithm of normalized probability of an n-th best probability value with a respective threshold, counting a number of the logarithms that exceed the respective threshold and generating, for each of the plurality of symbols, a score corresponding to the number. The method may also include calculating a moving average of the scores, and comparing the calculated moving average with an output threshold and flagging a just received one of the plurality of symbols as corrupted based upon the comparison.

Abstract translation: 描述了在接收机处识别受损的接收信号的方法。 接收到的信号可以包括符号。 每个符号可以具有与其相关联的伽罗瓦域的值。 接收机可以被配置为存储用于多个符号中的每一个的归一化概率质量函数的对数和对应的伽罗瓦域值。 归一化概率质量函数可以相对于多个符号的给定符号的最大概率质量函数被归一化。 该方法可以包括对于多个符号中的每一个，比较具有相应阈值的第n个最佳概率值的归一化概率的对数，对超过相应阈值的对数进行计数，并且对于每个 多个符号，一个分数对应的数字。 该方法还可以包括计算分数的移动平均值，以及将计算出的移动平均值与输出阈值进行比较，并且基于比较将多个符号中刚刚接收到的符号标记为已损坏。

公开(公告)号：US20110305094A1

公开(公告)日：2011-12-15

申请号：US13156356

申请日：2011-06-09

Applicant: Maurizio Francesco Perroni ,  Giuseppe Castagna

Inventor： Maurizio Francesco Perroni ,  Giuseppe Castagna

IPC: G11C7/06 ,  G11C7/12

CPC classification number: G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/30 ,  G11C16/3436

Abstract: An electrically programmable non-volatile memory device includes a plurality of memory cells, a plurality of lines for selectively biasing the memory cells, reconnection circuitry for reconnecting a pair of selected lines having different voltages, and a controller for controlling the memory device. The reconnection means includes a discharge circuit for discharging one of the selected lines being at the higher voltage in absolute value, an equalization circuit for equalizing the selected lines, a comparator circuit for measuring an indication of a voltage difference between the selected lines, and an evaluation circuit responsive to an enabling signal from the controller for activating the discharge circuit until an absolute value of the voltage difference exceeds a threshold value and for disabling the discharge circuit and enabling the equalization circuit when the absolute value of the voltage difference reaches the threshold value.

Abstract translation: 电可编程非易失性存储器件包括多个存储器单元，用于选择性地偏置存储单元的多条线，用于重新连接一对具有不同电压的选定线的重新连接电路，以及用于控制存储器件的控制器。 重新连接装置包括一个放电电路，用于将绝对值中较高电压的所选择的一条线放电，用于均衡所选择的线的均衡电路，用于测量所选择的线之间的电压差的指示的比较器电路和 评估电路响应于来自控制器的使能信号，用于激活放电电路，直到电压差的绝对值超过阈值，并且当电压差的绝对值达到阈值时禁用放电电路并使能均衡电路 。

公开(公告)号：US20110267891A1

公开(公告)日：2011-11-03

申请号：US13095025

申请日：2011-04-27

Applicant: Enrico Castaldo ,  Antonio Conte ,  Gianbattista Lo Giudice ,  Stefania Rinaldi

Inventor： Enrico Castaldo ,  Antonio Conte ,  Gianbattista Lo Giudice ,  Stefania Rinaldi

IPC: G11C16/06 ,  G11C16/10

CPC classification number: G11C16/30 ,  G11C16/12

Abstract: An electrically programmable non-volatile memory device is proposed. The memory device includes a plurality of memory cells and a driver circuit for driving the memory cells; the driver circuit includes programming means for providing a first programming voltage and a second programming voltage to a set of selected memory cells for programming the selected memory cells; the first programming voltage requires a first transient period for reaching a first target value thereof. In the solution according to an embodiment of the present invention, the programming means includes means for maintaining the second programming voltage substantially equal to the first programming voltage during a second transient period being required by the second programming voltage to reach a second target value thereof.

Abstract translation: 提出了一种电可编程非易失性存储器件。 存储装置包括多个存储单元和用于驱动存储单元的驱动电路; 所述驱动器电路包括用于向所选择的存储器单元的集合提供第一编程电压和第二编程电压的编程装置，用于对所选择的存储器单元进行编程; 第一编程电压需要用于达到其第一目标值的第一瞬态周期。 在根据本发明的实施例的解决方案中，编程装置包括用于在第二编程电压需要第二编程电压以达到其第二目标值的第二过渡时段期间将第二编程电压基本上等于第一编程电压的装置。

公开(公告)号：US20110193556A1

公开(公告)日：2011-08-11

申请号：US13021573

申请日：2011-02-04

Applicant: Dario Paci ,  Caterina Riva ,  Marco Morelli

Inventor： Dario Paci ,  Caterina Riva ,  Marco Morelli

IPC: G01R33/06

CPC classification number: G01R33/07

Abstract: An integrated magnetic sensor formed in a body including a substrate of semiconductor material, which integrates a Hall cell. A trench is formed in the body, for example, on the back of the substrate, and is delimited by lateral surface portions that extend in a direction transverse to the main face of the body. The trench has a depth in a direction perpendicular to the main face that is much greater than its width in a direction parallel to the main face of the body, between the lateral surface portions. A concentrator made of ferromagnetic material is formed within the trench and is constituted by two ferromagnetic regions, which are set at a distance apart from one another and extend along the lateral surface portions of the trench towards the first Hall cell.

Abstract translation: 一种形成在包括半导体材料的基板的主体中的集成磁传感器，其集成了霍尔单元。 在主体中形成沟槽，例如在基板的背面，并且由横向于主体的主面的方向延伸的侧面部分限定。 所述沟槽在垂直于所述主面的方向上的深度大于在所述侧表面部分之间平行于所述主体的主面的方向上的宽度。 由铁磁材料制成的集中器形成在沟槽内并且由两个铁磁区域构成，两个铁磁区域被设置成彼此间隔开一定距离并且沿沟槽的侧表面部分朝向第一霍尔室延伸。

公开(公告)号：US20110158016A1

公开(公告)日：2011-06-30

申请号：US12960355

申请日：2010-12-03

Applicant: Danilo Rimondi ,  Carolina Selva

Inventor： Danilo Rimondi ,  Carolina Selva

IPC: G11C29/00

CPC classification number: G11C29/08 ,  G11C11/41 ,  G11C29/02 ,  G11C29/022 ,  G11C29/025 ,  G11C29/026 ,  G11C29/24 ,  G11C29/44 ,  G11C2029/0401

Abstract: A method for testing a memory device. The memory device includes a matrix of memory cells having a plurality of rows and columns; the matrix includes a plurality of rows of operative memory cells each one for storing a variable value and at least one row of auxiliary memory cells each one storing a fixed value. The memory device further includes writing circuitry for writing selected values into the operative memory cells, and reading circuitry for reading the values being stored from the operative or auxiliary memory cells. The method includes reading output values from the row of auxiliary memory cells, determining a malfunctioning of the memory device in response to a missing match of the output values with the fixed values, determining a cause of the malfunctioning according to a pattern of reading errors between the output values and the corresponding fixed values, and providing a signal indicative of the cause of the malfunctioning.

Abstract translation: 一种用于测试存储器件的方法。 存储器件包括具有多个行和列的存储器单元的矩阵; 矩阵包括多行操作存储单元，每行存储单元用于存储可变值，并且每行至少一行辅助存储单元存储固定值。 存储器件还包括用于将选定值写入操作存储单元的写入电路，以及用于读取从操作或辅助存储器单元存储的值的读取电路。 该方法包括从辅助存储单元行读取输出值，响应于输出值与固定值的丢失匹配来确定存储器件的故障，根据读出错误的模式确定故障原因 输出值和相应的固定值，并提供指示故障原因的信号。

公开(公告)号：US20110157777A1

公开(公告)日：2011-06-30

申请号：US12972613

申请日：2010-12-20

Applicant: Alessandro Dundulachi

Inventor： Alessandro Dundulachi

IPC: H01G4/06 ,  H01G9/00

CPC classification number: H01L23/5223 ,  H01L28/40 ,  H01L28/86 ,  H01L2924/0002 ,  Y10T29/413 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49158 ,  H01L2924/00

Abstract: A method for producing an integrated device including a capacitor. The method includes the steps of providing a functional substrate including functional circuits of the integrated device, forming a first conductive layer including a first plate of the capacitor on the functional substrate, forming a layer of insulating material including a dielectric layer of the capacitor on a portion of the first conductive layer corresponding to the first plate, forming a second conductive layer including a second plate of the capacitor and functional connections to the functional circuits on a portion of the layer of insulating material corresponding to the dielectric layer, forming a protective layer of insulating material covering the second plate and the functional connections, forming a first contact for contacting the first plate, and forming a second contact and functional contacts for contacting the second plate and the functional connections, respectively, through the protective layer.

Abstract translation: 一种用于制造包括电容器的集成器件的方法。 该方法包括以下步骤：提供包括集成器件的功能电路的功能衬底，在功能衬底上形成包括电容器的第一板的第一导电层，形成包含电容器的电介质层的绝缘材料层 所述第一导电层的对应于所述第一板的部分形成包括所述电容器的第二板的第二导电层和与所述电介质层对应的所述绝缘材料层的一部分上的功能电路的功能连接，形成保护层 覆盖第二板和功能连接的绝缘材料，形成用于接触第一板的第一触点，以及形成第二触点和分别通过保护层接触第二板和功能连接的功能触点。