公开(公告)号：US20050286636A1

公开(公告)日：2005-12-29

申请号：US11136293

申请日：2005-05-24

Applicant: Marina Nicolas

Inventor： Marina Nicolas

IPC: H04N7/01 ,  H04N5/14 ,  H04N7/26 ,  H04B1/66 ,  H04N7/12 ,  H04N9/64 ,  H04N11/02 ,  H04N11/04

CPC classification number: H04N19/00703 ,  H04N5/145 ,  H04N7/014 ,  H04N19/51 ,  H04N19/521 ,  H04N19/56

Abstract: A motion estimation method and device are provided for processing images to be inserted, between a preceding original image and a following original image, into a sequence of images. Each image is divided into pixel blocks associated with motion vectors. For a current block of an image being processed, motion vectors associated with blocks of the image being processed and/or associated with blocks of a processed image are selected. Candidate vectors are generated from selected motion vectors. An error is calculated for each candidate vector. A penalty is determined for a subset of candidate vectors on the basis of the values of the pixels of the pixel block in the preceding original image from which the candidate motion vector points to the current block and/or on the basis of the values of the pixels of the pixel block in the following original image to which the candidate motion vector points from the current block.

Abstract translation: 提供了一种运动估计方法和装置，用于将先前的原始图像和下一个原始图像之间的待插入图像处理成图像序列。 每个图像被分成与运动矢量相关联的像素块。 对于正在处理的图像的当前块，选择与被处理图像的块正在处理和/或关联的图像的块相关联的运动矢量。 从选定的运动矢量生成候选向量。 为每个候选向量计算一个错误。 基于候选运动矢量指向当前块的先前原始图像中的像素块的像素值和/或基于当前块的值，确定候选矢量子集的惩罚 下一原始图像中的像素块的像素，候选运动矢量指向的当前块。

公开(公告)号：US20050245043A1

公开(公告)日：2005-11-03

申请号：US11110359

申请日：2005-04-20

Applicant: Alexandre Martin ,  Davy Villanueva ,  Frederic Salvetti

Inventor： Alexandre Martin ,  Davy Villanueva ,  Frederic Salvetti

IPC: H01L21/76 ,  H01L21/764 ,  H01L21/8234 ,  H01L27/08 ,  H01L27/088

CPC classification number: H01L21/764

Abstract: A method is provided for fabricating an integrated circuit. According to the method, hollow isolating trenches are produced within a substrate, and active components are produced in and on active areas of the substrate that are between the trenches. The trenches are produced in an initial phase carried out before production of the active components and a final phase carried out after production of the active components. In the initial phase, trenches are formed in the substrate, and the trenches are filled with a fill material. In the final phase, the active components are encapsulated, accesses are created through the encapsulation material to each filled trench, the fill material is removed through each access, and the opening of each trench is plugged through the corresponding access. Also provided is an integrated that includes hollow isolating trenches within a substrate.

Abstract translation: 提供了一种用于制造集成电路的方法。 根据该方法，在衬底内产生中空隔离沟槽，并且在沟槽之间的衬底的有源区域中和其上产生有源元件。 沟槽在生产活性组分之前进行的初始阶段产生，并且在生产活性组分后进行最后阶段。 在初始阶段，在衬底中形成沟槽，并且用填充材料填充沟槽。 在最后阶段，活性组分被封装，通过封装材料产生对每个填充的沟槽的访问，通过每个进入去除填充材料，并且每个沟槽的开口通过相应的访问被堵塞。 还提供了一种集成的，其包括衬底内的中空隔离沟槽。

公开(公告)号：US20050218981A1

公开(公告)日：2005-10-06

申请号：US11096798

申请日：2005-03-31

Applicant: Paolo Gatti ,  Marc Sabut

Inventor： Paolo Gatti ,  Marc Sabut

IPC: H03F3/45

CPC classification number: H03F3/45475 ,  H03F3/45179 ,  H03F2203/45521

Abstract: A differential amplifier having a first and second output terminals and receiving an input signal at an input terminal. The amplifier comprises a first amplifier having a first input connected to the input terminal, a second input and a first output connected together to the first output terminal, and a second output connected to the second output terminal, the first amplifier reproducing the input signal on the first output. The amplifier comprises a second amplifier having a first input receiving a reference signal and a second input connected to the output terminals by resistive elements and controlling the provision by the first amplifier on the second output of a signal such that the signals received at the first and second inputs of the second amplifier are equal.

Abstract translation: 一种具有第一和第二输出端并在输入端接收输入信号的差分放大器。 放大器包括：第一放大器，其具有连接到输入端的第一输入端，第二输入端和与第一输出端子连接在一起的第一输出端，​​以及连接到第二输出端子的第二输出端，第一放大器将输入信号再现在 第一个输出。 所述放大器包括具有接收参考信号的第一输入端的第二放大器和由电阻元件连接到所述输出端子的第二输入端，并且控制所述第一放大器在所述第二输出端提供的信号，使得在所述第一和 第二放大器的第二输入相等。

公开(公告)号：US20050208895A1

公开(公告)日：2005-09-22

申请号：US10919796

申请日：2004-08-17

Applicant: Pierre Busson ,  Bruno Paille

Inventor： Pierre Busson ,  Bruno Paille

IPC: H04L5/06 ,  H04L25/03 ,  H04L27/26 ,  H04B7/00

CPC classification number: H04L5/06 ,  H04L27/265 ,  H04L2025/03414 ,  H04L2025/03522

Abstract: In a calibration phase for a tuner of the DZIF type, N calibration frequency signals are generated at an input of a filter. The N calibration frequency signals have N calibration frequencies corresponding respectively after transposition to N analysis frequencies at an input of a Fourier transform. An amplitude and a phase of a corresponding point at an output of the Fourier transform are calculated for each analysis frequency. In a reception phase, each of the outputs of the Fourier transform is corrected with an inverse of the corresponding amplitude and opposite the corresponding phase calculated in the calibration phase.

Abstract translation: 在DZIF型调谐器的校准阶段，N个校准频率信号在滤波器的输入端产生。 N个校准频率信号在傅立叶变换的输入处转换到N个分析频率之后分别具有N个校准频率。 对于每个分析频率计算在傅立叶变换的输出处的对应点的振幅和相位。 在接收阶段，傅立叶变换的每个输出用对应的幅度的倒数校正，与在校准阶段计算出的相应的相位相反。

公开(公告)号：US20050186918A1

公开(公告)日：2005-08-25

申请号：US11036180

申请日：2005-01-14

Applicant: Serge Ramet ,  Pascal Triaire ,  Philippe Jouen

Inventor： Serge Ramet ,  Pascal Triaire ,  Philippe Jouen

IPC: H03L7/23 ,  H04L27/36 ,  H04B1/40 ,  H01Q11/12 ,  H04B1/04

CPC classification number: H04L27/362 ,  H03L7/23

Abstract: The present invention relates to an RF integrated circuit comprising a frequency synthesizer and a QAM modulator for modulating a baseband signal of frequency FBB, the frequency synthesizer supplying to the QAM modulator an output signal of frequency F1 adjustable with a frequency step ΔF1, for forming a carrier signal of the QAM modulator. According to the present invention, the frequency synthesizer is a Vernier effect frequency synthesizer comprising an auxiliary frequency synthesizer supplying an auxiliary signal of frequency F2 adjustable with a frequency step ΔF2 and a main frequency synthesizer having a phase-locked loop bandwidth at least two times higher than the frequency step ΔF2 of the auxiliary signal.

Abstract translation: 本发明涉及一种RF集成电路，其包括频率合成器和用于调制频率F BBB的基带信号的QAM调制器，频率合成器向QAM调制器提供频率为F 1的可调整的输出信号 具有用于形成QAM调制器的载波信号的频率步长ΔF1。 根据本发明，频率合成器是一种游标效应频率合成器，其包括辅助频率合成器，该辅助频率合成器提供频率为F 2的辅助信号，该频率F 2可用频率步长ΔF2调节，主频率合成器具有至少两个锁相环带宽 高于辅助信号的频率步长ΔF2。

公开(公告)号：US06928530B2

公开(公告)日：2005-08-09

申请号：US10081740

申请日：2002-02-22

Applicant: Yvon Bahout

Inventor： Yvon Bahout

IPC: G11C11/413 ,  G06F12/02 ,  G11C8/04 ,  G11C11/41 ,  G06F9/42

CPC classification number: G11C8/04

Abstract: A memory implementing an incremental address counter is sequentially read. An address jump includes detecting an address jump signal, incrementing the incremental address counter, and reading the content of the memory at the incremented address. The content read at the incremented address is transferred into the incremental address counter, and the content of the memory is read at the address contained in the incremental address counter.

Abstract translation: 依次读取实现增量地址计数器的存储器。 地址跳转包括检测地址跳转信号，递增增量地址计数器以及以递增的地址读取存储器的内容。 在增量地址读取的内容被传送到增量地址计数器，并且在包含在增量地址计数器中的地址读取存储器的内容。

公开(公告)号：US06928021B2

公开(公告)日：2005-08-09

申请号：US10638949

申请日：2003-08-11

Applicant: Stéphane Pecheyran ,  Jean-Michel Moragues ,  Benjamin Duval

Inventor： Stéphane Pecheyran ,  Jean-Michel Moragues ,  Benjamin Duval

IPC: G11C17/16 ,  G11C17/18 ,  G11C7/00

CPC classification number: G11C17/18 ,  G11C17/16

Abstract: An anti-fuse transistor includes a source, a drain and a well connected together, and a gate. A method for programming the anti-fuse transistor includes applying a reference potential to the gate, and applying a high potential greater than the reference potential to the drain of the anti-fuse transistor. A first access transistor is connected to the anti-fuse transistor. The first access transistor includes a drain connected to the source of the anti-fuse transistor, and a source for receiving the high potential. Applying the high potential to the drain of the anti-fuse transistor includes turning on the first access transistor.

Abstract translation: 反熔丝晶体管包括源极，漏极和阱连接在一起的栅极。 一种用于对抗熔丝晶体管进行编程的方法，包括向栅极施加参考电位，并将大于参考电位的高电位施加到反熔丝晶体管的漏极。 第一存取晶体管连接到反熔丝晶体管。 第一存取晶体管包括连接到反熔丝晶体管的源极的漏极和用于接收高电位的源极。 将高电位施加到反熔丝晶体管的漏极包括接通第一存取晶体管。

公开(公告)号：US06917116B2

公开(公告)日：2005-07-12

申请号：US10714442

申请日：2003-11-14

Applicant: Srdjan Kordic ,  Céline Roussel ,  Alain Inard

Inventor： Srdjan Kordic ,  Céline Roussel ,  Alain Inard

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/48

CPC classification number: H01L21/768 ,  H01L21/76838 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electrical connection device between two conducting tracks of an integrated circuit comprises a first conducting connection between the two tracks. The device further comprises an additional interface of one of the two tracks, different from the interface of the track with the first connection and different from the lateral interface of the track with an insulating material parallel to the flow direction of the electric current in the track. The additional interface is placed at some distance from the first connection which is substantially less than the width of the track. The additional interface may be obtained by placing at least a second conducting connection between the two tracks, or by placing at least one rib in the track, or by placing notches on at least one of the faces of the track.

Abstract translation: 集成电路的两个导电轨道之间的电连接装置包括两个轨道之间的第一导电连接。 该装置还包括两个轨道中的一个的附加接口，其不同于具有第一连接的轨道的界面，并且不同于轨道的横向界面，其绝缘材料与轨道中的电流的流动方向平行 。 附加接口被放置在距离第一连接一定距离处，该距离基本上小于轨道的宽度。 可以通过在两个轨道之间放置至少第二导电连接，或通过在轨道中放置至少一个肋，或者通过在轨道的至少一个面上放置凹口来获得附加界面。

公开(公告)号：US06914304B2

公开(公告)日：2005-07-05

申请号：US10867285

申请日：2004-06-14

Applicant: Pierre Busson ,  Pierre-Olivier Jouffre ,  Bernard Louis-Gavet

Inventor： Pierre Busson ,  Pierre-Olivier Jouffre ,  Bernard Louis-Gavet

IPC: H01L23/36 ,  H01L23/60 ,  H01L23/62 ,  H02H9/00

CPC classification number: H01L23/60 ,  H01L24/48 ,  H01L2224/05553 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48237 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/10161 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: The electronic component, comprises an integrated circuit incorporating several separate functional blocks within a semiconductor substrate, and electrostatic discharge protection means. These electrostatic discharge protection means comprise several separate metal discharge rails (GNDi) placed above the substrate (SB) and respectively associated with the plurality of functional blocks (CRi), all these metal discharge rails being mutually unconnected electrically within the integrated circuit (CI) but connected electrically via an electrical connection (FLi) external to the integrated circuit to one and the same ground plane (SLG) forming a ground reference for the electrostatic discharges, this ground plane (SLG) being located outside the integrated circuit (CI), and possibly being a heat slug.

Abstract translation: 该电子部件包括在半导体衬底内并入几个单独功能块的集成电路和静电放电保护装置。 这些静电放电保护装置包括放置在衬底（SB）上方并分别与多个功能块（CRi）分别相关联的多个单独的金属放电导轨（GNDi），所有这些金属放电导轨在集成电路（CI）内都是电连接的， 但是通过集成电路外部的电连接（FLi）电连接到形成用于静电放电的接地基准的同一接地平面（SLG），该接地平面（SLG）位于集成电路（CI）外部， 并可能是一个热塞。

公开(公告)号：US20050138403A1

公开(公告)日：2005-06-23

申请号：US10966833

申请日：2004-10-14

Applicant: Marcus Volp ,  Claude Anguille

Inventor： Marcus Volp ,  Claude Anguille

IPC: G06F21/24 ,  H04L9/08 ,  H04L9/12 ,  H04L9/14 ,  H04L9/18 ,  H04L9/00 ,  G06F12/14

CPC classification number: H04L9/0662 ,  H04L9/0894 ,  H04L2209/12

Abstract: For the encryption of data to be stored in a memory external to a circuit, provision is made to store in the external memory encrypted data words in association with an initialization vector and a key identifier associated with a secret key that has served to encrypt same.

Abstract translation: 为了对要存储在电路外部的存储器中的数据进行加密，提供与外部存储器相关联的加密数据字与初始化向量相关联的密钥标识符，以及与已经被加密的秘密密钥相关联的密钥标识符。