Magnetic Logic Units Configured to Measure Magnetic Field Direction

    公开(公告)号:US20130241536A1

    公开(公告)日:2013-09-19

    申请号:US13787585

    申请日:2013-03-06

    Abstract: An apparatus includes circuits, a field line configured to generate a magnetic field based on an input, a sensing module configured to determine a parameter of each circuit, and a magnetic field direction determination module configured to determine an angular orientation of the apparatus relative to an external magnetic field based on the parameter. Each circuit includes multiple magnetic tunnel junctions. Each magnetic tunnel junction includes a storage layer having a storage magnetization direction and a sense layer having a sense magnetization direction configured based on the magnetic field. Each magnetic tunnel junction is configured such that the sense magnetization direction and a resistance of the magnetic tunnel junction vary based on the external magnetic field. The parameter varies based on the resistances of the multiple magnetic tunnel junctions. The magnetic field direction determination module is implemented in at least one of a memory or a processing device.

    Apparatus, System, And Method For Matching Patterns With An Ultra Fast Check Engine
    22.
    发明申请
    Apparatus, System, And Method For Matching Patterns With An Ultra Fast Check Engine 有权
    用超快速检测引擎匹配模式的装置,系统和方法

    公开(公告)号:US20120143889A1

    公开(公告)日:2012-06-07

    申请号:US13309369

    申请日:2011-12-01

    Abstract: A check engine includes a plurality of comparators each including a first directional characteristic aligned to store at least one reference bit included in a set of reference bits, and a second directional characteristic aligned to present at least one target bit included in a set of target bits. Each of the plurality of comparators is configured to produce an output representing a level of matching between the at least one target bit and the at least one reference bit, based on a relative alignment between the first directional characteristic and the second directional characteristic. The check engine is configured such that the outputs of the plurality of comparators are combined to produce a combined output. The check engine is configured to determine that the set of target bits matches the set of reference bits based on the combined output of the plurality of comparators.

    Abstract translation: 检查引擎包括多个比较器,每个比较器包括对齐以存储包括在一组参考比特中的至少一个参考比特的第一方向特性,以及对准以呈现包括在一组目标比特中的至少一个目标比特的第二方向特性 。 多个比较器中的每一个被配置为基于第一方向特性和第二方向特性之间的相对对准来产生表示所述至少一个目标位和所述至少一个参考位之间的匹配水平的输出。 检查引擎被配置为使得多个比较器的输出被组合以产生组合输出。 检查引擎被配置为基于多个比较器的组合输出来确定目标比特的集合与参考比特集匹配。

    Magnetic Logic Units Configured as Analog Circuit Building Blocks
    24.
    发明申请
    Magnetic Logic Units Configured as Analog Circuit Building Blocks 有权
    配置为模拟电路构建块的逻辑单元

    公开(公告)号:US20150214952A1

    公开(公告)日:2015-07-30

    申请号:US14606960

    申请日:2015-01-27

    CPC classification number: H03K19/18 G11C11/1659 G11C11/1673 G11C11/1675

    Abstract: A circuit includes a magnetic logic unit including input terminals, output terminals, a field line, and magnetic tunnel junctions (MTJs). The field line electrically connects a first and a second input terminal, and is configured to generate a magnetic field based on an input to at least one of the first and the second input terminal. The input is based on an analog input to the circuit. Each MTJ is electrically connected to a first output terminal and a second output terminal, and is configured such that an output of at least one of the first and the second output terminal varies in response to a combined resistance of the MTJs. The resistance of each of the MTJs varies based on the magnetic field. The circuit is configured to generate an analog output based on the output of at least one of the first and the second output terminal.

    Abstract translation: 电路包括包括输入端子,输出端子,场线和磁隧道结(MTJ)的磁逻辑单元。 场线电连接第一和第二输入端子,并且被配置为基于对第一和第二输入端子中的至少一个的输入产生磁场。 输入是基于电路的模拟输入。 每个MTJ电连接到第一输出端和第二输出端,并且被配置为使得第一和第二输出端中的至少一个的输出响应于MTJ的组合电阻而变化。 每个MTJ的电阻根据磁场而变化。 电路被配置为基于第一和第二输出端子中的至少一个的输出来产生模拟输出。

    Magnetic Logic Units Configured to Measure Magnetic Field Direction
    25.
    发明申请
    Magnetic Logic Units Configured to Measure Magnetic Field Direction 有权
    配置用于测量磁场方向的磁逻辑单元

    公开(公告)号:US20150077095A1

    公开(公告)日:2015-03-19

    申请号:US14552302

    申请日:2014-11-24

    Abstract: An apparatus includes circuits, a field line configured to generate a magnetic field based on an input, a sensing module configured to determine a parameter of each circuit, and a magnetic field direction determination module configured to determine an angular orientation of the apparatus relative to an external magnetic field based on the parameter. Each circuit includes multiple magnetic tunnel junctions. Each magnetic tunnel junction includes a storage layer having a storage magnetization direction and a sense layer having a sense magnetization direction configured based on the magnetic field. Each magnetic tunnel junction is configured such that the sense magnetization direction and a resistance of the magnetic tunnel junction vary based on the external magnetic field. The parameter varies based on the resistances of the multiple magnetic tunnel junctions. The magnetic field direction determination module is implemented in at least one of a memory or a processing device.

    Abstract translation: 一种装置包括电路,被配置为基于输入产生磁场的场线,被配置为确定每个电路的参数的感测模块以及被配置为确定所述装置相对于所述电路的角度定向的磁场方向确定模块 基于参数的外部磁场。 每个电路包括多个磁隧道结。 每个磁性隧道结包括具有存储磁化方向的存储层和具有基于磁场配置的感测磁化方向的感测层。 每个磁性隧道结被构造成使得感应磁化方向和磁性隧道结的电阻基于外部磁场而变化。 该参数根据多个磁隧道结的电阻而变化。 磁场方向确定模块在存储器或处理装置中的至少一个中实现。

    Apparatus, System, and Method for Matching Patterns with an Ultra Fast Check Engine
    26.
    发明申请
    Apparatus, System, and Method for Matching Patterns with an Ultra Fast Check Engine 审中-公开
    使用超快速检查引擎匹配模式的装置,系统和方法

    公开(公告)号:US20140195883A1

    公开(公告)日:2014-07-10

    申请号:US14207066

    申请日:2014-03-12

    Abstract: A check engine includes a plurality of comparators each including a first directional characteristic aligned to store at least one reference bit included in a set of reference bits, and a second directional characteristic aligned to present at least one target bit included in a set of target bits. Each of the plurality of comparators is configured to produce an output representing a level of matching between the at least one target bit and the at least one reference bit, based on a relative alignment between the first directional characteristic and the second directional characteristic. The check engine is configured such that the outputs of the plurality of comparators are combined to produce a combined output. The check engine is configured to determine that the set of target bits matches the set of reference bits based on the combined output of the plurality of comparators.

    Abstract translation: 检查引擎包括多个比较器,每个比较器包括对齐以存储包括在一组参考比特中的至少一个参考比特的第一方向特性,以及对准以呈现包括在一组目标比特中的至少一个目标比特的第二方向特性 。 多个比较器中的每一个被配置为基于第一方向特性和第二方向特性之间的相对对准来产生表示所述至少一个目标位和所述至少一个参考位之间的匹配水平的输出。 检查引擎被配置为使得多个比较器的输出被组合以产生组合输出。 检查引擎被配置为基于多个比较器的组合输出来确定目标比特的集合与参考比特集匹配。

    Memory Devices with Magnetic Random Access Memory (MRAM) Cells and Associated Structures for connecting the MRAM Cells
    27.
    发明申请
    Memory Devices with Magnetic Random Access Memory (MRAM) Cells and Associated Structures for connecting the MRAM Cells 有权
    具有磁性随机存取存储器(MRAM)的存储器件和用于连接MRAM单元的相关结构

    公开(公告)号:US20140110802A1

    公开(公告)日:2014-04-24

    申请号:US13657708

    申请日:2012-10-22

    Abstract: A memory device includes a magnetic layer including a plurality of magnetic random access memory (MRAM) cells, a first conductive layer, a layer including a strap connecting MRAM cells included in the plurality of MRAM cells, and a second conductive layer. The first conductive layer includes a conductive portion electrically connected to at least one of the plurality of MRAM cells, and a field line configured to write data to the at least one of the plurality of MRAM cells. The second conductive layer includes a conductive interconnect electrically connected to the at least one of the plurality of MRAM cells, where the magnetic layer is disposed between the first conductive layer and the second conductive layer. At least one of the plurality of MRAM cells is directly attached to the second conductive layer and the strap.

    Abstract translation: 存储器件包括包括多个磁随机存取存储器(MRAM)单元的磁性层,第一导电层,包括连接多个MRAM单元中包括的MRAM单元的带的层和第二导电层。 第一导电层包括电连接到多个MRAM单元中的至少一个的导电部分,以及被配置为将数据写入多个MRAM单元中的至少一个的场线。 第二导电层包括电连接到多个MRAM单元中的至少一个MRAM单元的导电互连,其中磁性层设置在第一导电层和第二导电层之间。 多个MRAM单元中的至少一个直接附接到第二导电层和带。

    Memory devices with series-interconnected magnetic random access memory cells
    28.
    发明授权
    Memory devices with series-interconnected magnetic random access memory cells 有权
    具有串联互连磁存储单元的存储器件

    公开(公告)号:US08625336B2

    公开(公告)日:2014-01-07

    申请号:US13023441

    申请日:2011-02-08

    CPC classification number: G11C11/1675 G11C11/1659 G11C11/1673

    Abstract: A memory device includes magnetic random access memory (“MRAM”) cells that are electrically connected in series, each one of the MRAM cells having a storage magnetization direction and a sense magnetization direction. During a write operation, multiple ones of the MRAM cells are written in parallel by switching the storage magnetization directions of the MRAM cells. During a read operation, a particular one of the MRAM cells is read by varying the sense magnetization direction of the particular one of the MRAM cells, relative to the storage magnetization direction of the particular one of the MRAM cells.

    Abstract translation: 存储器件包括串联电连接的磁随机存取存储器(“MRAM”)单元,每个MRAM单元具有存储磁化方向和感测磁化方向。 在写入操作期间,通过切换MRAM单元的存储磁化方向来并行写入多个MRAM单元。 在读取操作期间,通过相对于特定MRAM单元的存储磁化方向改变特定MRAM单元的感测磁化方向来读取特定的一个MRAM单元。

    Magnetic random access memory devices including multi-bit cells
    29.
    发明授权
    Magnetic random access memory devices including multi-bit cells 有权
    包括多位单元的磁性随机存取存储器件

    公开(公告)号:US08576615B2

    公开(公告)日:2013-11-05

    申请号:US13158312

    申请日:2011-06-10

    CPC classification number: G11C11/5607 G11C11/161 G11C11/1673 G11C11/1675

    Abstract: A magnetic random access memory (“MRAM”) cell includes: (1) a first magnetic layer having a first magnetization direction and a magnetic anisotropy axis; (2) a second magnetic layer having a second magnetization direction; and (3) a spacer layer disposed between the first magnetic layer and the second magnetic layer. The MRAM cell also includes a field line magnetically coupled to the MRAM cell and configured to induce a write magnetic field along a magnetic field axis, and the magnetic anisotropy axis is tilted relative to the magnetic field axis. During a write operation, the first magnetization direction is switchable between m directions to store data corresponding to one of m logic states, with m>2, at least one of the m directions is aligned relative to the magnetic anisotropy axis, and at least another one of the m directions is aligned relative to the magnetic field axis.

    Abstract translation: 磁性随机存取存储器(“MRAM”)单元包括:(1)具有第一磁化方向和磁各向异性轴的第一磁性层; (2)具有第二磁化方向的第二磁性层; 和(3)设置在第一磁性层和第二磁性层之间的间隔层。 MRAM单元还包括磁耦合到MRAM单元并且被配置为沿着磁场轴诱导写磁场的磁场线,并且磁各向异性轴相对于磁场轴倾斜。 在写入操作期间,第一磁化方向可以在m个方向之间切换以存储对应于m个逻辑状态中的一个的数据,其中m≥2,m个方向中的至少一个相对于磁各向异性轴对准,并且至少另一个 m个方向中的一个相对于磁场轴线对准。

    Magnetic Logic Units Configured as an Amplifier
    30.
    发明申请
    Magnetic Logic Units Configured as an Amplifier 有权
    配置为放大器的磁性逻辑单元

    公开(公告)号:US20130241636A1

    公开(公告)日:2013-09-19

    申请号:US13769156

    申请日:2013-02-15

    Abstract: An apparatus includes a circuit and a field line. The circuit includes a magnetic tunnel junction including a storage layer and a sense layer. The field line is configured to generate a magnetic field based on an input signal, where the magnetic tunnel junction is configured such that a magnetization direction of the sense layer and a resistance of the magnetic tunnel junction vary based on the magnetic field. The circuit is configured to amplify the input signal to generate an output signal that varies in response to the resistance of the magnetic tunnel junction.

    Abstract translation: 一种装置包括电路和场线。 该电路包括一个包括存储层和感应层的磁性隧道结。 场线被配置为基于输入信号产生磁场,其中磁性隧道结被配置为使得感测层的磁化方向和磁性隧道结的电阻基于磁场而变化。 电路被配置为放大输入信号以产生响应于磁性隧道结的电阻而变化的输出信号。

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