公开(公告)号：US12222826B2

公开(公告)日：2025-02-11

申请号：US18104458

申请日：2023-02-01

Applicant: Arm Limited

Inventor： Ashok Kumar Tummala ,  FNU Parshant ,  Rishabh Jain ,  Apurva Patel ,  Surabhi Garg ,  Sai Kumar Marri

IPC: G06F11/07 ,  G06F11/20

Abstract: A mechanism for error containment in a data processing system includes receiving a transaction request at a gateway between a host and a device, allocating an entry for the request in a local request tracker of the gateway and sending a link request, to a port of the gateway. In response to an isolation trigger, the port is moved into isolation by completing in-process requests with entries in the tracker and locking the entries. On receiving a response to an in-process request while the port is in isolation, the response is dropped, the associated entry is unlocked, and allocation of the entry is enabled. A completion response is sent to the requester without dispatching a new link request to the port. When requests are completed, the system is quiesced, locked entries are unlocked, and the port is moved out of isolation.

公开(公告)号：US20250037228A1

公开(公告)日：2025-01-30

申请号：US18785254

申请日：2024-07-26

Applicant: Arm Limited

Inventor： Olof Henrik Uhrenholt

IPC: G06T1/20

Abstract: When performing rendering in a tile-based graphics processor that comprises plural rendering processors, different regions of the render output are allocated to different ones of the rendering processors for processing. The processing of the render output is tracked to determine when a portion of the render output that is still to be allocated to the rendering processors for processing falls below a threshold, and when it is determined that a portion of the render output that is still to be allocated to the rendering processors for processing falls below the threshold, smaller regions of the render output are thereafter allocated to the rendering processors for processing.

公开(公告)号：US12210408B2

公开(公告)日：2025-01-28

申请号：US17999780

申请日：2021-05-27

Applicant: Arm Limited

Inventor： Jacob Paul Bramley ,  Georgia Kouveli ,  Martyn Maurice Capewell ,  Pierre Denis Michel Langlois

IPC: G06F11/07 ,  G06F12/14

Abstract: An apparatus has tag checking circuitry responsive to a target address to: identify a guard tag stored in a memory system in association with a block of one or more memory locations, the block containing a target memory location identified by the target address, perform a tag check based on the guard tag and an address tag associated with the target address, and in response to detecting a mismatch in the tag check, perform an error response action. The apparatus also has tag mapping storage circuitry to store mapping information indicative of a mapping between guard tag values and corresponding address tag values. The tag checking circuitry remaps at least one of the guard tag and the address tag based on the mapping information stored by the tag mapping storage circuitry to generate a remapped tag for use in the tag check.

公开(公告)号：US20250030833A1

公开(公告)日：2025-01-23

申请号：US18353229

申请日：2023-07-17

Applicant: Arm Limited

Inventor： Dumidu Sanjaya TALAGALA ,  Nerhun YILDIZ ,  David HANWELL

IPC: H04N17/00 ,  G06T7/00 ,  G06T7/11 ,  G06V10/98 ,  G06V20/56

Abstract: A method of data processing in a data processing system comprising a computer vision system. The method comprises obtaining image data representative of a plurality of pixels of an image, the image data comprising a plurality of pixel intensity values respectively representing said pixels. The method comprises identifying one or more compromised pixel intensity values in the plurality of pixel intensity values. The method comprises generating sensor defect state data relating to the identified compromised pixel intensity values. The method comprises performing, using the computer vision system, a feature recognition process on the image data. The method comprises performing an action based on the sensor defect state data.

公开(公告)号：US20250029215A1

公开(公告)日：2025-01-23

申请号：US18774004

申请日：2024-07-16

Applicant: Arm Limited

Inventor： Dumidu Sanjaya Talagala ,  David Hanwell

IPC: G06T5/70 ,  G06V10/60

Abstract: A method of image processing. The method comprises obtaining a set of image data, the set being associated with one or more parameters representative of one or more image capture characteristics for the set and comprising pixel intensity values representing image pixels having respective pixel locations in an image. The method comprises, for a given pixel intensity value in the set: determining an estimated noise value based on at least: the one or more parameters associated with the set, and a representative intensity value derived from one or more pixel intensity values in the set. The method comprises associating the estimated noise value with the given pixel intensity value.

公开(公告)号：US20250028933A1

公开(公告)日：2025-01-23

申请号：US18356091

申请日：2023-07-20

Applicant: Arm Limited

Inventor： Gerti Tuzi ,  Dibakar Gope

IPC: G06N3/045 ,  G06N3/08

Abstract: Example methods, apparatuses, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, using one or more computing devices to estimate an execution latency of a candidate neural network in a neural network architecture search (NAS) process.

公开(公告)号：US12205663B2

公开(公告)日：2025-01-21

申请号：US16506662

申请日：2019-07-09

Applicant: Arm Limited

Inventor： Steve Ngueya Wandji ,  El Mehdi Boujamaa ,  Cyrille Nicolas Dray

IPC: G11C5/14 ,  G11C11/16 ,  H02M3/07

Abstract: In a particular implementation, a circuit comprises: a first branch comprising a first transistor, where the first branch is configured to generate a first voltage; a second branch comprising a second transistor, where the second branch is configured to generate a second voltage; and a comparator configured to generate an output signal based on a comparison of the first and second voltages. Also, the output signal may be configured to regulate an output voltage of one or more negative charge pump circuits coupled to the circuit.

公开(公告)号：US12204562B2

公开(公告)日：2025-01-21

申请号：US18152946

申请日：2023-01-11

Applicant: Arm Limited

Inventor： Thibaut Elie Lanois ,  Houdhaifa Bouzguarrou ,  Guillaume Bolbenes

IPC: G06F16/28 ,  G06F16/22 ,  G06F16/2457

Abstract: An apparatus has a data storage structure to store data items tagged by respective tag values and stores, in association with each data item, a respective tag group identifier to identify other data items having a same tag value within a collection of data items. The apparatus also has tag match circuitry to identify one or more hitting data items. Prioritisation circuitry is provided to select candidate data items which, relative to any other data items in the particular collection of data items having the same tag group identifier as the selected candidate data item is favoured according to an ordering of the data items. The prioritisation circuitry selects the one or more candidate data items before the identification of the hitting data items is available from the tag match circuitry. Data item selection circuitry selects a candidate data item for which the tag match circuitry detected a match.

公开(公告)号：US20250021487A1

公开(公告)日：2025-01-16

申请号：US18711242

申请日：2022-04-28

Applicant: Arm Limited

Inventor： Richard Roy Grisenthwaite

IPC: G06F12/1009

Abstract: Memory management circuitry (28) supports two-stage address translation based on a stage-1 and stage-2 translation table structures. Stage-2 access permission information specified by a stage-2 translation table entry has an encoding specifying whether a corresponding memory region has a partially-read-only permission indicating that write requests to the memory region corresponding to the target intermediate address, issued when processing circuitry (4) is in a predetermined execution state, are permitted for a restricted subset of write request types (including metadata-updating write requests for updating access tracking metadata in translation table entries) but prohibited for other write request types. The memory management circuitry (28) rejects a memory access request when the stage-2 access permission information of a corresponding stage-2 translation table entry specifies the partially-read-only permission and the memory access request is a write request, other than the restricted subset of write request types, issued in the predetermined execution state.

公开(公告)号：US20250021480A1

公开(公告)日：2025-01-16

申请号：US18350217

申请日：2023-07-11

Applicant: Arm Limited

Inventor： Natalya BONDARENKO ,  Stefano GHIGGINI ,  Kamil GARIFULLIN ,  Fabian GRUBER ,  . ABHISHEK RAJA ,  Devin S. LAFFORD

IPC: G06F12/0811 ,  G06F12/0862 ,  G06F12/0871

Abstract: Apparatuses, methods, systems, and chip-containing products are disclosed, which relate to an arrangement comprising a level N cache level and a level M cache level, where M is greater than N. The level N cache level comprises a plurality of linefill slots and performs a slot allocation procedure in response to a lookup miss in dependence on a linefill slot occupancy criterion. The slot allocation procedure comprises allocation of an available slot of the plurality of slots to a pending linefill request generated in response to the lookup miss. The level N cache level effects a modification of the slot allocation procedure in dependence on the linefill slot occupancy criterion and is responsive to the linefill slot occupancy criterion being fulfilled to cause a linefill delegation action to be instructed to the level M cache level.