公开(公告)号：US20120229497A1

公开(公告)日：2012-09-13

申请号：US13043183

申请日：2011-03-08

Applicant: Brijesh Tripathi ,  Michael Frank

Inventor： Brijesh Tripathi ,  Michael Frank

IPC: G09G5/02

CPC classification number: G09G3/2037 ,  G09G3/2051 ,  G09G3/2066 ,  G09G2320/0266

Abstract: Devices and methods for dynamic dithering are provided. For example, an electronic device according to an embodiment may include image processing circuitry that operates on higher-bit-depth image data and a display panel that displays lower-bit-depth image data. To obtain the lower-bit-depth image data, the image processing circuitry may perform dynamic dithering on the higher-bit-depth image data. Such dynamic dithering may involve dithering frames of the higher-bit-depth image data based at least in part on respective rounding threshold values.

Abstract translation: 提供动态抖动的设备和方法。 例如，根据实施例的电子设备可以包括对高位深度图像数据进行操作的图像处理电路和显示低位深度图像数据的显示面板。 为了获得低位深度图像数据，图像处理电路可以对高位深度图像数据执行动态抖动。 这种动态抖动可以至少部分地基于相应的舍入阈值来涉及高位深度图像数据的抖动帧。

公开(公告)号：US08155316B1

公开(公告)日：2012-04-10

申请号：US11678733

申请日：2007-02-26

Applicant: Duncan A. Riach ,  Brijesh Tripathi

Inventor： Duncan A. Riach ,  Brijesh Tripathi

IPC: H04N7/167 ,  H04N1/44

CPC classification number: G06T1/60 ,  G09G5/001 ,  G09G5/363 ,  G09G5/39 ,  G09G2360/18

Abstract: A method of displaying an image includes generating a contract in the display engine, transferring the contract to the memory controller before the end of a sweep, generating a contract amendment in response to changes in the display engine, transferring the contract amendment to the memory controller, making a decision whether the contract amendment can be processed, fetching data from the memory controller according to the contract incorporating the contract amendment if the decision is that the contract amendment can be processed, sending the fetched data to the display engine in an isochronous stream; and processing the fetched data using the display engine.

Abstract translation: 显示图像的方法包括在显示引擎中生成合同，在结束扫描之前将合同转移到存储器控制器，响应于显示引擎的变化产生合同修改，将合同修改转移到存储器控制器 作出决定是否可以处理合同修正案，如果决定是可以处理合同修正案，则根据包含合同修订的合同从存储器控制器获取数据，将获取的数据以同步流发送到显示引擎 ; 并使用显示引擎来处理所获取的数据。

公开(公告)号：US07426594B1

公开(公告)日：2008-09-16

申请号：US10961574

申请日：2004-10-08

Applicant: Duncan A. Riach ,  Brijesh Tripathi

Inventor： Duncan A. Riach ,  Brijesh Tripathi

IPC: G06F12/00 ,  G06F13/14 ,  G06F12/02

CPC classification number: G06F13/1605 ,  G09G5/001 ,  G09G5/363

Abstract: Apparatus, system, and method for arbitrating between memory requests are described. In one embodiment, a processing apparatus includes a memory request generator configured to generate memory requests specifying data for respective presentation elements. The memory request generator is configured to assign priorities to the memory requests based on a presentation order of the presentation elements. The processing apparatus also includes a memory request arbiter connected to the memory request generator. The memory request arbiter is configured to issue the memory requests based on the priorities assigned to the memory requests.

Abstract translation: 描述用于在存储器请求之间进行仲裁的装置，系统和方法。 在一个实施例中，处理装置包括存储器请求生成器，其被配置为生成为各个呈现元素指定数据的存储器请求。 存储器请求生成器被配置为基于呈现元素的呈现顺序为存储器请求分配优先级。 处理装置还包括连接到存储器请求发生器的存储器请求仲裁器。 存储器请求仲裁器被配置为基于分配给存储器请求的优先级来发布存储器请求。

公开(公告)号：US07221369B1

公开(公告)日：2007-05-22

申请号：US10903403

申请日：2004-07-29

Applicant: Brijesh Tripathi ,  Wayne Douglas Young ,  Adam E. Levinthal ,  Stephen M. Ryan

Inventor： Brijesh Tripathi ,  Wayne Douglas Young ,  Adam E. Levinthal ,  Stephen M. Ryan

IPC: G06F15/00 ,  G06F13/00 ,  G09G5/36 ,  G06T1/20 ,  G06T1/00 ,  G06T15/00 ,  G06F15/167 ,  G06F13/28

CPC classification number: G06T1/60 ,  G06F13/4059 ,  G09G5/363

Abstract: Apparatus, system, and method for delivering data to multiple memory clients are described. In one embodiment, a graphics processing apparatus includes an output pipeline including a set of memory clients. The graphics processing apparatus also includes a memory controller connected to the output pipeline. The memory controller is configured to retrieve data requested by respective ones of the set of memory clients from a memory. The graphics processing apparatus further includes a buffering module connected between the memory controller and the output pipeline. The buffering module includes a unitary buffer and a buffer controller connected to the unitary buffer. The buffer controller is configured to coordinate storage of the data in the unitary buffer, and the buffer controller is configured to coordinate delivery of the data from the unitary buffer to respective ones of the set of memory clients.

Abstract translation: 描述了将数据传送到多个存储器客户端的装置，系统和方法。 在一个实施例中，图形处理装置包括包括一组存储器客户端的输出流水线。 图形处理装置还包括连接到输出管线的存储器控​​制器。 存储器控制器被配置为从存储器检索由存储器客户端集合中的相应的一组请求的数据。 图形处理装置还包括连接在存储器控制器和输出管线之间的缓冲模块。 缓冲模块包括连接到整体缓冲器的整体缓冲器和缓冲器控制器。 缓冲器控制器被配置为协调数据在单一缓冲器中的存储，并且缓冲器控制器被配置为协调将数据从单一缓冲器传送到该组存储器客户端中的相应的一个。

公开(公告)号：US09355585B2

公开(公告)日：2016-05-31

申请号：US13438409

申请日：2012-04-03

Applicant: Brijesh Tripathi ,  Jean-Pierre Guillou

Inventor： Brijesh Tripathi ,  Jean-Pierre Guillou

IPC: G06F3/038 ,  G09G3/20

CPC classification number: G06F3/041 ,  G06T19/006 ,  G09G3/20 ,  G09G2320/029 ,  G09G2320/0606 ,  G09G2320/0613 ,  G09G2320/103 ,  G09G2330/02 ,  G09G2330/021 ,  G09G2340/0435 ,  G09G2354/00 ,  G09G2360/18

Abstract: An electronic device may be provided with a display. The display may be a variable frame rate display capable of adaptively adjusting a frame rate at which display frames are displayed in response to information associated with the current state of operation of the device. The information may be gathered using control circuitry in the electronic device. The control circuitry may gather the information for adjusting the frame rate by monitoring the electronic device power supply configuration, other device components, the type of content to be displayed, and user-input signals. The control circuitry may adjust the frame rate based on the gathered information by increasing or decreasing the frame rate. The control circuitry may be formed as a portion of display control circuitry for the device such as a display driver integrated circuit or may be formed as a portion of storage and processing circuitry external to the display.

Abstract translation: 电子设备可以设置有显示器。 显示器可以是能够响应于与设备的当前操作状态相关联的信息自适应地调整显示帧显示的帧速率的可变帧率显示器。 可以使用电子设备中的控制电路来收集信息。 控制电路可以通过监视电子设备电源配置，其他设备组件，要显示的内容的类型和用户输入信号来收集用于调整帧速率的信息。 控制电路可以通过增加或减少帧速率来基于所收集的信息来调整帧速率。 控制电路可以形成为诸如显示器驱动器集成电路的装置的显示控制电路的一部分，或者可以形成为显示器外部的存储和处理电路的一部分。

公开(公告)号：US09123278B2

公开(公告)日：2015-09-01

申请号：US13404733

申请日：2012-02-24

Applicant: Brijesh Tripathi ,  Craig M. Okruhlica ,  Nitin Bhargava

Inventor： Brijesh Tripathi ,  Craig M. Okruhlica ,  Nitin Bhargava

IPC: G09G5/02 ,  G09G5/391 ,  H04N9/64 ,  G09G5/373

CPC classification number: G09G5/02 ,  G09G5/373 ,  G09G5/391 ,  G09G2340/02 ,  G09G2340/0428

Abstract: Methods and graphics processing pipelines for performing inline chroma downsampling of pixel data. The graphics processing pipeline includes a chroma downsampling unit for performing buffer-free downsampling of chroma pixel components. A vertical column of chroma pixel components is received in each clock cycle by the chroma downsampling unit, and downsampled chroma pixel components are generated on every clock cycle or every other clock cycle. Vertical, horizontal, and vertical and horizontal downsampling can be performed without buffers by the chroma downsampling unit. A programmable configuration register in the chroma downsampling unit determines the type of downsampling that is implemented.

Abstract translation: 用于执行像素数据的内联色度下采样的方法和图形处理流水线。 图形处理流水线包括用于执行色度像素分量的无缓冲下采样的色度下采样单元。 通过色度下采样单元在每个时钟周期中接收垂直色度像素分量列，并且在每个时钟周期或每隔一个时钟周期产生下采样色度像素分量。 垂直，水平，垂直和水平向下采样可以通过色度下采样单元进行，无需缓冲器。 色度下采样单元中的可编程配置寄存器决定了所采用的下采样类型。

公开(公告)号：US08963946B2

公开(公告)日：2015-02-24

申请号：US13238023

申请日：2011-09-21

Applicant: Brijesh Tripathi ,  Craig M. Okruhlica ,  Wolfgang Roethig

Inventor： Brijesh Tripathi ,  Craig M. Okruhlica ,  Wolfgang Roethig

IPC: G06F12/10 ,  G09G5/04 ,  G09G3/20

CPC classification number: G09G5/04 ,  G09G3/2051 ,  G09G2320/0271

Abstract: A dither unit with a programmable kernel matrix in which each indexed location/entry may store one or more dither values. Each dither value in a respective entry of the kernel matrix may correspond to the number of bits that are truncated during dithering. During dithering of each pixel of an image, entries in the kernel matrix may be indexed according to the relative coordinates of the pixel within the image. A dither value for the pixel may be selected from the indexed entry based on the truncated least significant bits of the pixel component value. When the kernel matrix is storing more than one dither value per entry, the dither value may be selected based further on the number of truncated least significant bits. A dithered pixel component value may then be generated according to the dither value and the remaining most significant bits of the pixel component value.

Abstract translation: 具有可编程内核矩阵的抖动单元，其中每个索引的位置/条目可以存储一个或多个抖动值。 内核矩阵的相应条目中的每个抖动值可以对应于在抖动期间被截断的位数。 在图像的每个像素的抖动期间，内核矩阵中的条目可以根据图像内的像素的相对坐标进行索引。 可以基于像素分量值的截断的最低有效位从索引条目中选择像素的抖动值。 当内核矩阵每个条目存储多于一个抖动值时，可以进一步基于截断的最低有效位的数量来选择抖动值。 然后可以根据抖动值和像素分量值的剩余最高有效位来产生抖动像素分量值。

公开(公告)号：US08773455B2

公开(公告)日：2014-07-08

申请号：US13207805

申请日：2011-08-11

Applicant: Brijesh Tripathi ,  Nitin Bhargava

Inventor： Brijesh Tripathi ,  Nitin Bhargava

IPC: G09G5/00 ,  G09G5/02 ,  G09G1/28 ,  G06F13/14 ,  G06T15/00 ,  G09G5/10 ,  H04N9/44 ,  H04N11/00 ,  H03M1/12 ,  H04N9/12 ,  G06F5/00 ,  G06F15/00 ,  G09G5/395 ,  G06F13/24 ,  G06F15/76 ,  G06F9/40 ,  G06F9/00 ,  G09G5/18 ,  G09G3/20

CPC classification number: G09G5/395 ,  G09G3/2048 ,  G09G5/18 ,  G09G2340/125 ,  G09G2360/125 ,  G09G2370/10

Abstract: A display controller may include an RGB Interface module and a display port module, which may both use a target-master interface, in which the data receiving module pops pixels from the data sourcing module, and generates the HSync, VSync, and VBI timing signals. A dither module may be instantiated between the RGB interface module and display port module to perform dithering. The dither module may use a source-master interface, in which data signals and data valid signals are issued by the data sourcing module. In order to avoid having to use a large storage capacity FIFO with the dither module, a control unit may issue interface signals to the RGB Interface module and display port module, and clock-gate the dither module, to allow the data signals and data valid signals to properly interface with the RBG interface module and display port module, and provide data flow from the RGB interface module to the dither module to the display port module.

Abstract translation: 显示控制器可以包括RGB接口模块和显示器端口模块，其可以使用目标主机接口，其中数据接收模块从数据采集模块中弹出像素，并且生成HSync，VSync和VBI定时信号 。 可以在RGB接口模块和显示端口模块之间实例化抖动模块以执行抖动。 抖动模块可以使用源 - 主接口，其中数据信号和数据有效信号由数据采集模块发出。 为了避免使用具有抖动模块的大容量FIFO，控制单元可以向RGB接口模块和显示端口模块发出接口信号，并对抖动模块进行时钟门控，以允许数据信号和数据有效 信号与RBG接口模块和显示端口模块正确接口，并提供从RGB接口模块到抖动模块到显示端口模块的数据流。

公开(公告)号：US08725918B2

公开(公告)日：2014-05-13

申请号：US13494179

申请日：2012-06-12

Applicant: Anup K. Sharma ,  Scott P. Krueger ,  James M. Hollabaugh ,  Roberto G. Yepez ,  Mitchell D. Adler ,  Brijesh Tripathi ,  Jeffrey J. Terlizzi

Inventor： Anup K. Sharma ,  Scott P. Krueger ,  James M. Hollabaugh ,  Roberto G. Yepez ,  Mitchell D. Adler ,  Brijesh Tripathi ,  Jeffrey J. Terlizzi

IPC: G06F13/38 ,  G09G3/34

CPC classification number: G06F3/1431 ,  G06F3/14 ,  G06F13/385 ,  G06F13/4013 ,  G06F13/4018 ,  G06T1/60 ,  Y02D10/14 ,  Y02D10/151

Abstract: In an embodiment, a host computing device includes an internal display and also includes a connector to connect to an external display. A cable is provided to connect to the connector and to connect to the external display. The cable includes video processing capabilities. For example, the cable may include a memory configured to store a frame buffer. The frame buffer may store a frame of video data for further processing by the video processing device in the cable. The video processing device may manipulate the frame in a variety of ways, e.g. scaling, rotating, gamma correction, dither correction, etc.

公开(公告)号：US20140075117A1

公开(公告)日：2014-03-13

申请号：US13610633

申请日：2012-09-11

Applicant: Brijesh Tripathi ,  Peter F. Holland

Inventor： Brijesh Tripathi ,  Peter F. Holland

IPC: G06F12/08

CPC classification number: G06F12/0888 ,  G06F2212/455 ,  G09G5/001 ,  G09G5/363 ,  G09G5/39 ,  G09G5/395 ,  G09G2360/121 ,  G09G2360/123

Abstract: A system and method for efficiently allocating data in a memory hierarchy. A system includes a memory controller for controlling accesses to a memory and a display controller for processing video frame data. The memory controller includes a cache capable of storing data read from the memory. A given video frame may be processed by the display controller and presented on a respective display screen. During processing, control logic within the display controller sends multiple memory access requests to the memory controller with cache hint information. For the frame data, the cache hint information may alternate between (i) indicating to store frame data read in response to respective requests in the memory cache and (ii) indicating to not store the frame data read in response to respective requests in the memory cache.

Abstract translation: 一种用于在存储器层级中有效分配数据的系统和方法。 系统包括用于控制对存储器的访问的存储器控​​制器和用于处理视频帧数据的显示控制器。 存储器控制器包括能够存储从存储器读取的数据的高速缓存器。 给定的视频帧可以由显示控制器处理并呈现在相应的显示屏幕上。 在处理期间，显示控制器内的控制逻辑使用高速缓存提示信息向存储器控制器发送多个存储器访问请求。 对于帧数据，缓存提示信息可以在（i）指示存储响应于存储器高速缓存中的相应请求而读取的帧数据和（ii）指示不存储响应于存储器中的各个请求而读取的帧数据的交替 缓存。