公开(公告)号：US20100230726A1

公开(公告)日：2010-09-16

申请号：US12786003

申请日：2010-05-24

Applicant: Cheng Hung Lee

Inventor： Cheng Hung Lee

IPC: H01L27/10

CPC classification number: H01L27/0207 ,  H01L27/105

Abstract: An integrated circuit (IC) chip includes a first memory cell array block having a first metal layer containing at least two power lines, and a second memory cell array block containing at least two power lines independent of each other, wherein all the power lines on the first metal layer serving the first memory cell array block do not extend into the second memory cell array block, and all the power lines on the first metal layer serving the second memory cell array block do not extend into the first memory cell array block.

Abstract translation: 集成电路（IC）芯片包括具有包含至少两条电源线的第一金属层的第一存储单元阵列块和包含彼此独立的至少两条电源线的第二存储单元阵列块，其中所有电源线在 服务于第一存储单元阵列块的第一金属层不延伸到第二存储单元阵列块中，并且服务于第二存储单元阵列块的第一金属层上的所有电力线不延伸到第一存储单元阵列块中。

公开(公告)号：US20100103719A1

公开(公告)日：2010-04-29

申请号：US12259009

申请日：2008-10-27

Applicant: Cheng Hung Lee

Inventor： Cheng Hung Lee

IPC: G11C11/00 ,  G11C7/00

CPC classification number: G11C11/412

Abstract: An integrated circuit device includes a first word-line; a second word-line; a first bit-line; and a static random access memory (SRAM) cell. The SRAM cell includes a storage node; a pull-up transistor having a source/drain region coupled to the storage node; a pull-down transistor having a source/drain region coupled to the storage node; a first pass-gate transistor comprising a gate coupled to the first word-line; and a second pass-gate transistor including a gate coupled to the second word-line. Each of the first and the second pass-gate transistors includes a first source/drain region coupled to the first bit-line, and a second source/drain region coupled to the storage node.

Abstract translation: 集成电路装置包括第一字线; 第二个字线; 第一个位线 和静态随机存取存储器（SRAM）单元。 SRAM单元包括存储节点; 具有耦合到存储节点的源极/漏极区域的上拉晶体管; 具有耦合到存储节点的源极/漏极区域的下拉晶体管; 第一通过栅晶体管，包括耦合到第一字线的栅极; 以及包括耦合到第二字线的栅极的第二栅极晶体管。 第一和第二栅极晶体管中的每一个包括耦合到第一位线的第一源极/漏极区域和耦合到存储节点的第二源极/漏极区域。

公开(公告)号：US07660486B2

公开(公告)日：2010-02-09

申请号：US11456516

申请日：2006-07-10

Applicant: Tsu-mu Chang ,  Cheng-hung Lee

Inventor： Tsu-mu Chang ,  Cheng-hung Lee

IPC: G06K9/32 ,  G09G5/00

CPC classification number: G06T3/4023

Abstract: A method of resizing an image having a plurality of data unit blocks is disclosed. Each data unit block is a pixel matrix. The method includes the steps of generating column pseudo-pixel matrix corresponding to a data unit block, decimating/interpolating the data unit block in column direction to generate a scaled column-pixel matrix, filtering the scaled column-pixel matrix and the column pseudo-pixel matrix to generate a filtered column-pixel matrix, storing the filtered column-pixel matrix in a first buffer, generating a row pseudo-pixel matrix corresponding to the filtered column-pixel matrix stored in the first buffer, decimating/interpolating each the filtered column-pixel matrix to generate a scaled row-pixel matrix, and filtering the scaled row-pixel matrix and the row pseudo-pixel matrix to generate a resized row-pixel matrix.

Abstract translation: 公开了一种调整具有多个数据单元块的图像大小的方法。 每个数据单元块是一个像素矩阵。 该方法包括以下步骤：产生与数据单元块相对应的列伪像素矩阵，在列方向抽取/内插数据单元块以产生缩放的列像素矩阵，对经比较的列像素矩阵和列伪像素矩阵进行滤波， 像素矩阵以产生滤波后的列像素矩阵，将滤波后的列像素矩阵存储在第一缓冲器中，产生与存储在第一缓冲器中的滤波后的列像素矩阵相对应的行伪像素矩阵，抽取/内插每个滤波的 列像素矩阵以生成缩放的行像素矩阵，并且对经缩放的行像素矩阵和行伪像素矩阵进行滤波以生成调整大小的行像素矩阵。

公开(公告)号：US07505345B2

公开(公告)日：2009-03-17

申请号：US11811659

申请日：2007-06-11

Applicant: Chia Wei Wang ,  Cheng Hung Lee ,  Hung-Jen Liao ,  Fu-Chieh Hsu

Inventor： Chia Wei Wang ,  Cheng Hung Lee ,  Hung-Jen Liao ,  Fu-Chieh Hsu

IPC: G11C7/02

CPC classification number: G11C11/418 ,  G11C8/08

Abstract: A circuit and method for providing a two phase word line pulse for use during access cycles in an SRAM memory with improved operating margins. A first and a second timing circuit are provided and a word line voltage suppression circuit is provided to reduce the voltage on the active word lines in a first phase of a word line pulse, and to allow the word lines to rise to a second, unsuppressed voltage in a second phase of the word line pulse, responsive to the first and second timing circuits. The first and second timing circuits observe the bit lines voltage discharge and provide control signals active when the bit lines are discharged past certain thresholds, these signals control the voltage suppression circuit. Operating margins for the SRAM are therefore improved. Methods for operating an SRAM using a two phase word line pulse are provided.

Abstract translation: 一种电路和方法，用于在具有改进的操作余量的SRAM存储器中的访问周期期间提供两相字线脉冲。 提供第一和第二定时电路，并且提供字线电压抑制电路以减小字线脉冲的第一相中有效字线上的电压，并允许字线上升到第二，未压缩 响应于第一和第二定时电路在字线脉冲的第二相位中的电压。 第一和第二定时电路观察位线电压放电，并且当位线经过某些阈值时提供控制信号有效，这些信号控制电压抑制电路。 因此，SRAM的工作裕度得到改善。 提供了使用两相字线脉冲来操作SRAM的方法。

公开(公告)号：US07502277B2

公开(公告)日：2009-03-10

申请号：US11599934

申请日：2006-11-15

Applicant: Ching-Wei Wu ,  Cheng Hung Lee ,  Hung-Jen Liao

Inventor： Ching-Wei Wu ,  Cheng Hung Lee ,  Hung-Jen Liao

IPC: G11C8/00

CPC classification number: G11C11/412 ,  G11C8/08

Abstract: This invention discloses an integrated circuit, which comprises a first and a second pull-down circuit controlled by a first and second signal, respectively, and coupled between a first node and a low voltage power supply (Vss), and a controllable pull-up circuit coupled between the first node and a complimentary high voltage power supply (Vcc), wherein when either the first or second signal is asserted to a predetermined logic state, the first node is pulled down to a logic LOW state.

Abstract translation: 本发明公开了一种集成电路，其包括分别由第一和第二信号控制并耦合在第一节点和低电压电源（Vss）之间的第一和第二下拉电路以及可控上拉 耦合在第一节点和互补高压电源（Vcc）之间的电路，其中当第一或第二信号被确定到预定逻辑状态时，第一节点被下拉到逻辑低电平状态。

公开(公告)号：US20080112213A1

公开(公告)日：2008-05-15

申请号：US11599934

申请日：2006-11-15

Applicant: Ching-Wei Wu ,  Cheng Hung Lee ,  Hung-Jen Liao

Inventor： Ching-Wei Wu ,  Cheng Hung Lee ,  Hung-Jen Liao

IPC: G11C11/00 ,  G11C7/12 ,  G11C8/00

CPC classification number: G11C11/412 ,  G11C8/08

Abstract: This invention discloses an integrated circuit, which comprises a first and a second pull-down circuit controlled by a first and second signal, respectively, and coupled between a first node and a low voltage power supply (Vss), and a controllable pull-up circuit coupled between the first node and a complimentary high voltage power supply (Vcc), wherein when either the first or second signal is asserted to a predetermined logic state, the first node is pulled down to a logic LOW state.

Abstract translation: 本发明公开了一种集成电路，其包括分别由第一和第二信号控制并耦合在第一节点和低电压电源（Vss）之间的第一和第二下拉电路以及可控上拉 耦合在第一节点和互补高压电源（Vcc）之间的电路，其中当第一或第二信号被确定到预定逻辑状态时，第一节点被下拉到逻辑低电平状态。

公开(公告)号：US09099168B2

公开(公告)日：2015-08-04

申请号：US13616377

申请日：2012-09-14

Applicant: Hsu-Shun Chen ,  Cheng-Hung Lee ,  Hong-Chen Cheng ,  Chung-Yi Wu

Inventor： Hsu-Shun Chen ,  Cheng-Hung Lee ,  Hong-Chen Cheng ,  Chung-Yi Wu

IPC: G11C8/08 ,  G11C11/413

CPC classification number: G11C8/08 ,  G11C11/413

Abstract: An integrated circuit includes a positive power supply node, a current tracking circuit, and a current mirroring circuit including a plurality of current paths coupled in parallel. The currents of the plurality of current paths mirror a current of the current tracking circuit. The current mirroring circuit is configured to turn off the plurality of current paths one-by-one in response to a reduction in a positive power supply voltage on the positive power supply node. The integrated circuit further includes a charging node receiving a summation current of the plurality of current paths, wherein a voltage on the charging node is configured to increase through a charging of the summation current.

Abstract translation: 集成电路包括正电源节点，电流跟踪电路和包括并联耦合的多个电流路径的电流镜像电路。 多个电流通路的电流反映了电流跟踪电路的电流。 电流镜像电路被配置为响应于正电源节点上的正电源电压的减小而逐个关闭多个电流路径。 集成电路还包括接收多个电流路径的求和电流的充电节点，其中充电节点上的电压被配置为通过对和电流的充电而增加。

公开(公告)号：US08976611B2

公开(公告)日：2015-03-10

申请号：US13837614

申请日：2013-03-15

Applicant: Jung-Ping Yang ,  Chia-En Huang ,  Fu-An Wu ,  Chih-Chieh Chiu ,  Cheng Hung Lee

Inventor： Jung-Ping Yang ,  Chia-En Huang ,  Fu-An Wu ,  Chih-Chieh Chiu ,  Cheng Hung Lee

IPC: G11C7/00 ,  G11C7/06 ,  G06F17/50 ,  G11C7/10 ,  G11C7/12 ,  G11C11/419

CPC classification number: G11C7/065 ,  G06F17/5063 ,  G06F17/5081 ,  G11C7/1048 ,  G11C7/12 ,  G11C11/419

Abstract: A sensing amplifier for a memory device includes first and second nodes, an input device and an output device. The memory device includes first and second bit lines, and at least one memory cell coupled to the bit lines. The first and second nodes are coupled to the first and second bit lines, respectively. The input device is coupled to the first and second nodes and generates a first current pulling the first node toward a predetermined voltage in response to a first datum read out from the memory cell, and to generate a second current pulling the second node toward the predetermined voltage in response to a second datum read out from the memory cell. The output device is coupled to the first node to output the first or second datum read out from the memory cell. The first current is greater than the second current.

Abstract translation: 用于存储器件的感测放大器包括第一和第二节点，输入设备和输出设备。 存储器件包括第一和第二位线，以及耦合到位线的至少一个存储器单元。 第一和第二节点分别耦合到第一和第二位线。 输入设备耦合到第一和第二节点，并且响应于从存储器单元读出的第一数据产生第一电流将第一节点拉向预定电压，并且产生将第二节点拉向预定的第二电流的第二电流 响应于从存储器单元读出的第二数据的电压。 输出设备耦合到第一节点以输出从存储器单元读出的第一或第二数据。 第一个电流大于第二个电流。

公开(公告)号：US08947903B2

公开(公告)日：2015-02-03

申请号：US13178021

申请日：2011-07-07

Applicant: Cheng Hung Lee ,  XiuLi Yang ,  Liangbo Zhuang

Inventor： Cheng Hung Lee ,  XiuLi Yang ,  Liangbo Zhuang

IPC: G11C11/00 ,  G11C7/12 ,  G11C8/08 ,  G11C7/18

CPC classification number: G11C5/06 ,  G11C7/12 ,  G11C7/18 ,  G11C8/08 ,  G11C11/005

Abstract: A semiconductor memory chip that has word lines driven by respective word line drivers and bit lines to carry signals to respective bit line amplifiers/drivers with memory cells at intersections of the word lines and bit lines memory cells. The semiconductor memory chip including various memory cell types, the type of memory cell at an intersection based on a position of the intersection among the word lines and bit lines.

Abstract translation: 一种半导体存储器芯片，其具有由相应的字线驱动器和位线驱动的字线，以将信号传送到具有位线和位线存储器单元的交叉处的存储器单元的各个位线放大器/驱动器。 包括各种存储单元类型的半导体存储器芯片，基于字线和位线之间的交点的位置的交叉路口处的存储单元的类型。

公开(公告)号：US08587023B2

公开(公告)日：2013-11-19

申请号：US11137241

申请日：2005-05-25

Applicant: Cheng Hung Lee

Inventor： Cheng Hung Lee

IPC: H01L29/74

CPC classification number: H01L21/765 ,  H01L27/0629 ,  H01L27/0921

Abstract: A guard ring system is disclosed for protecting an integrated circuit comprising. It has a first guard ring area formed by a well in the substrate, a capacitor area formed within the first guard ring area which further includes two well contacts formed into the well and biased by a first supply voltage, and a dielectric layer placed between the two contacts on the well with its first side in contact with the well. A second supply voltage complementary to the first supply voltage is applied to a second side of the dielectric layer so that a voltage difference across the dielectric layer provides a local capacitance embedded therein.

Abstract translation: 公开了用于保护集成电路的保护环系统，包括： 它具有由衬底中的阱形成的第一保护环区域，形成在第一保护环区域内的电容器区域，其还包括形成在阱中并由第一电源电压偏置的两个阱触点，以及置于 井的两个接触点，其第一面与井接触。 与第一电源电压互补的第二电源电压被施加到电介质层的第二侧，使得跨介电层的电压差提供嵌入其中的局部电容。