公开(公告)号：US20060124979A1

公开(公告)日：2006-06-15

申请号：US11352179

申请日：2006-02-10

Applicant: Cheol-ju Yun ,  Sun-hoo Park

Inventor： Cheol-ju Yun ,  Sun-hoo Park

IPC: H01L29/94

CPC classification number: H01L27/0207 ,  H01L27/10808 ,  H01L27/10855 ,  H01L27/10885 ,  H01L28/91

Abstract: A DRAM memory cell includes a semiconductor substrate, an interlayer dielectric having storage node contact plugs that is formed on the semiconductor substrate, and storage node electrodes that are formed on the interlayer dielectric to contact the storage node contact plugs. The storage node contact plugs are formed such that an entrance portion is formed to be larger in linewidth than a contacting portions, and they are formed in gaps between the bit line structures. From a plan view perspective, the storage node electrodes of one column are offset from the storage node contact plugs in an adjacent column, such that the storage node electrodes are in a diagonal arrangement throughout the semiconductor substrate.

Abstract translation: DRAM存储单元包括半导体衬底，形成在半导体衬底上的存储节点接触插塞的层间电介质和形成在层间电介质上以与存储节点接触插头接触的存储节点电极。 存储节点接触插塞形成为使得入口部分形成为比接触部分更大的线宽，并且它们形成在位线结构之间的间隙中。 从平面图的观点来看，一列的存储节点电极偏离相邻列中的存储节点接触插塞，使得存储节点电极在贯穿整个半导体衬底的对角排列。

公开(公告)号：US07056786B2

公开(公告)日：2006-06-06

申请号：US10762380

申请日：2004-01-23

Applicant: Cheol-Ju Yun ,  Chang-Hyun Cho ,  Tae-Young Chung

Inventor： Cheol-Ju Yun ,  Chang-Hyun Cho ,  Tae-Young Chung

IPC: H01L21/8242

CPC classification number: H01L21/76897 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L28/91

Abstract: A self-aligned buried contact (BC) pair includes a substrate having diffusion regions; an oxide layer exposing a pair of diffusion regions formed on the substrate; bit lines formed between adjacent diffusion regions and on the oxide layer, each of the bit lines having bit line sidewall spacers formed on sidewalls thereof; a first interlayer dielectric (ILD) layer formed over the bit lines and the oxide layer; a pair of BC pads formed between adjacent bit lines and within the first ILD layer, each BC pad being aligned with one of the pair of exposed diffusion regions in the substrate; and a pair of capacitors, each of the pair of BC pads having one of the pair of capacitors formed thereon, wherein a pair of the bit line sidewall spacers is adjacent to each of the BC pads and the pair of bit line sidewall spacers has an asymmetrical shape.

Abstract translation: 自对准埋层接触（BC）对包括具有扩散区域的衬底; 暴露形成在所述基板上的一对扩散区域的氧化物层; 在相邻扩散区之间和氧化物层上形成的位线，每个位线在其侧壁上形成有位线侧壁间隔物; 形成在位线和氧化物层上的第一层间电介质（ILD）层; 一对BC焊盘，形成在相邻位线之间并且在第一ILD层内，每个BC焊盘与衬底中一对暴露的扩散区域中的一个对准; 和一对电容器，所述一对BC焊盘中的每一对具有形成在其上的一对电容器中的一个，其中一对位线侧壁间隔件与每个BC焊盘相邻，并且所述一对位线侧壁间隔件具有 不对称形状。

公开(公告)号：US20050218408A1

公开(公告)日：2005-10-06

申请号：US11096129

申请日：2005-03-31

Applicant: Cheol-ju Yun ,  Tae-young Chung ,  Dong-jun Lee

Inventor： Cheol-ju Yun ,  Tae-young Chung ,  Dong-jun Lee

IPC: H01L27/108 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L29/12

CPC classification number: H01L27/10888 ,  H01L21/76804 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10891

Abstract: A method of manufacturing a semiconductor device includes forming conductive structures on a substrate. Each of the conductive structures has a line shape that extends along a first direction parallel to the substrate. Insulating spacers are formed on upper sidewalls of the conductive structures. An insulating interlayer is formed that covers the conductive structures. A portion of the insulating interlayer between the conductive structures is etched to form a contact hole. An upper portion of the contact hole is larger than a lower portion thereof. The upper portion of the contact hole has a first width along the first direction and a second width along a second direction parallel to the substrate and substantially perpendicular to the first direction. The first width is substantially larger than the second width. The contact hole is filled with a conductive material to form a contact plug.

Abstract translation: 制造半导体器件的方法包括在衬底上形成导电结构。 每个导电结构具有沿平行于基板的第一方向延伸的线状。 绝缘垫片形成在导电结构的上侧壁上。 形成覆盖导电结构的绝缘中间层。 导电结构之间的绝缘中间层的一部分被蚀刻以形成接触孔。 接触孔的上部大于其下部。 接触孔的上部具有沿着第一方向的第一宽度和沿着平行于基底并基本上垂直于第一方向的第二方向的第二宽度。 第一宽度基本上大于第二宽度。 接触孔填充有导电材料以形成接触塞。

公开(公告)号：US20050186733A1

公开(公告)日：2005-08-25

申请号：US10938154

申请日：2004-09-10

Applicant: Cheol-Ju Yun ,  Tae-Young Chung

Inventor： Cheol-Ju Yun ,  Tae-Young Chung

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242

CPC classification number: H01L27/10885 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76897 ,  H01L27/10855

Abstract: According to some embodiments of the invention, a method of forming a self-aligned contact of a semiconductor device includes forming a plurality of conductive lines that are spaced apart from each other and pass over a plurality of conductive regions. An insulating layer is formed over and between the conductive lines. A plurality of contact holes are then formed to selectively expose the conductive regions by selectively removing the insulating layer without exposing the conductive lines. The contact holes are extended using an isotropic etching until the conductive lines begin to be exposed. Thereafter, contacts are formed in the contact holes such that the contacts are coupled to the conductive regions.

Abstract translation: 根据本发明的一些实施例，形成半导体器件的自对准接触的方法包括形成彼此间隔开并跨越多个导电区域的多条导线。 在导线之间和之间形成绝缘层。 然后形成多个接触孔，以通过选择性地去除绝缘层而不暴露导电线来选择性地暴露导电区域。 使用各向同性蚀刻使接触孔延伸，直到导线开始暴露。 此后，在接触孔中形成触点，使得触点耦合到导电区域。

公开(公告)号：US20050186732A1

公开(公告)日：2005-08-25

申请号：US11066842

申请日：2005-02-23

Applicant: Cheol-Ju Yun

Inventor： Cheol-Ju Yun

IPC: H01L27/108 ,  H01L21/20 ,  H01L21/285 ,  H01L21/60 ,  H01L21/8242

CPC classification number: H01L21/76897 ,  H01L21/28518 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10888

Abstract: According to some embodiments of the invention, semiconductor devices and DRAM cells have plug contact holes. Methods of forming the same include forming a channel-portion hole disposed in a semiconductor substrate. Lower portions of the plug contact holes between first and second word line patterns extend downward from the main surface of the semiconductor substrate, thereby reducing a contact resistance between plug patterns and electrode impurity regions. The DRAM cell having the plug contact holes can improve the current driving capability of a transistor and the refresh characteristics of a capacitor.

Abstract translation: 根据本发明的一些实施例，半导体器件和DRAM单元具有插头接触孔。 形成它们的方法包括形成设置在半导体衬底中的沟道部分孔。 第一和第二字线图案之间的插头接触孔的下部从半导体衬底的主表面向下延伸，从而减小插头图形与电极杂质区之间的接触电阻。 具有插头接触孔的DRAM单元可以提高晶体管的电流驱动能力和电容器的刷新特性。

公开(公告)号：US07557410B2

公开(公告)日：2009-07-07

申请号：US11769260

申请日：2007-06-27

Applicant: Jin-Woo Lee ,  Cheol-Ju Yun ,  Hyeoung-Won Seo

Inventor： Jin-Woo Lee ,  Cheol-Ju Yun ,  Hyeoung-Won Seo

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC classification number: H01L27/10814 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L28/91 ,  H01L29/6659

Abstract: A semiconductor device comprises a plurality of gate structures formed on a substrate, a gate spacer formed on a sidewall of the gate structures, a semiconductor pattern formed on the substrate between the gate structures, a first impurity region and a second impurity region formed in the semiconductor pattern and at surface portions of the substrate, respectively, wherein the first and second impurity regions include a first conductive type impurity, and a channel doping region surrounding the first impurity region, wherein the channel doping region includes a second conductive type impurity.

Abstract translation: 半导体器件包括形成在衬底上的多个栅极结构，形成在栅极结构的侧壁上的栅极间隔物，形成在栅极结构之间的衬底上的半导体图案，形成在栅极结构中的第一杂质区域和第二杂质区域 半导体图案和衬底的表面部分，其中第一和第二杂质区域包括第一导电类型杂质和围绕第一杂质区的沟道掺杂区域，其中沟道掺杂区域包括第二导电类型杂质。

公开(公告)号：US07482222B2

公开(公告)日：2009-01-27

申请号：US11769276

申请日：2007-06-27

Applicant: Jin-Woo Lee ,  Cheol-Ju Yun ,  Hyeoung-Won Seo

Inventor： Jin-Woo Lee ,  Cheol-Ju Yun ,  Hyeoung-Won Seo

IPC: H01L21/8242

CPC classification number: H01L27/10814 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L28/91 ,  H01L29/6659

Abstract: A semiconductor device comprises a plurality of gate structures formed on a substrate, a gate spacer formed on a sidewall of the gate structures, a semiconductor pattern formed on the substrate between the gate structures, a first impurity region and a second impurity region formed in the semiconductor pattern and at surface portions of the substrate, respectively, wherein the first and second impurity regions include a first conductive type impurity, and a channel doping region surrounding the first impurity region, wherein the channel doping region includes a second conductive type impurity.

Abstract translation: 半导体器件包括形成在衬底上的多个栅极结构，形成在栅极结构的侧壁上的栅极间隔物，形成在栅极结构之间的衬底上的半导体图案，形成在栅极结构中的第一杂质区域和第二杂质区域 半导体图案和衬底的表面部分，其中第一和第二杂质区域包括第一导电类型杂质和围绕第一杂质区的沟道掺杂区域，其中沟道掺杂区域包括第二导电类型杂质。

公开(公告)号：US07030439B2

公开(公告)日：2006-04-18

申请号：US10704514

申请日：2003-11-07

Applicant: Cheol-ju Yun ,  Sun-hoo Park

Inventor： Cheol-ju Yun ,  Sun-hoo Park

IPC: H01L27/108 ,  H01L29/94

CPC classification number: H01L27/0207 ,  H01L27/10808 ,  H01L27/10855 ,  H01L27/10885 ,  H01L28/91

Abstract: A DRAM memory cell includes a semiconductor substrate, an interlayer dielectric having storage node contact plugs that is formed on the semiconductor substrate, and storage node electrodes that are formed on the interlayer dielectric to contact the storage node contact plugs. The storage node contact plugs are formed such that an entrance portion is formed to be larger in linewidth than a contacting portions, and they are formed in gaps between the bit line structures. From a plan view perspective, the storage node electrodes of one column are offset from the storage node contact plugs in an adjacent column, such that the storage node electrodes are in a diagonal arrangement throughout the semiconductor substrate.

Abstract translation: DRAM存储单元包括半导体衬底，形成在半导体衬底上的存储节点接触插塞的层间电介质和形成在层间电介质上以与存储节点接触插头接触的存储节点电极。 存储节点接触插塞形成为使得入口部分形成为比接触部分更大的线宽，并且它们形成在位线结构之间的间隙中。 从平面图的观点来看，一列的存储节点电极偏离相邻列中的存储节点接触插塞，使得存储节点电极在贯穿整个半导体衬底的对角排列。

公开(公告)号：US06773338B2

公开(公告)日：2004-08-10

申请号：US10357471

申请日：2003-02-04

Applicant: Cheol-Ju Yun ,  Young-Min Kim

Inventor： Cheol-Ju Yun ,  Young-Min Kim

IPC: B24B100

CPC classification number: B24B37/32 ,  B24B49/04

Abstract: A polishing head and a chemical mechanical polishing apparatus having the polishing head including a plate having vacuum holes for transferring vacuum pumping force; a porous film having holes corresponding to the vacuum holes and attached to a lower surface of the plate; a retainer ring attached to the lower surface of the plate at an edge portion thereof and having a sloped surface; a clamp ring attached to the lower surface of the plate adjacent the retainer ring for clamping the retainer ring; an adjusting ring having a sloped surface parallel and in contact with the sloped surface of the retainer ring, the adjusting ring being installed between the retainer ring and the plate; and a diameter adjusting device for adjusting a diameter of the adjusting ring by moving the adjusting ring along the sloped surface of the retainer ring, thereby adjusting a height of the retainer ring.

Abstract translation: 一种抛光头和化学机械抛光装置，其具有包括具有用于传递真空抽吸力的真空孔的板的抛光头; 多孔膜，其具有与所述真空孔对应的孔，并且附着到所述板的下表面; 保持环在其边缘部分处附接到板的下表面并具有倾斜表面; 夹紧环，其附接到邻近保持环的板的下表面，用于夹持保持环; 调节环，其具有平行于所述保持环的倾斜表面的倾斜表面，所述调节环安装在所述保持环和所述板之间; 以及直径调节装置，用于通过沿着保持环的倾斜表面移动调节环来调节调节环的直径，从而调节保持环的高度。

公开(公告)号：US07547938B2

公开(公告)日：2009-06-16

申请号：US11954349

申请日：2007-12-12

Applicant: Cheol-ju Yun ,  Tae-young Chung ,  Dong-jun Lee

Inventor： Cheol-ju Yun ,  Tae-young Chung ,  Dong-jun Lee

IPC: H01L27/108 ,  H01L29/94

CPC classification number: H01L27/10888 ,  H01L21/76804 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10891

Abstract: A method of manufacturing a semiconductor device includes forming conductive structures on a substrate. Each of the conductive structures has a line shape that extends along a first direction parallel to the substrate. Insulating spacers are formed on upper sidewalls of the conductive structures. An insulating interlayer is formed that covers the conductive structures. A portion of the insulating interlayer between the conductive structures is etched to form a contact hole. An upper portion of the contact hole is larger than a lower portion thereof. The upper portion of the contact hole has a first width along the first direction and a second width along a second direction parallel to the substrate and substantially perpendicular to the first direction. The first width is substantially larger than the second width. The contact hole is filled with a conductive material to form a contact plug.

Abstract translation: 制造半导体器件的方法包括在衬底上形成导电结构。 每个导电结构具有沿平行于基板的第一方向延伸的线状。 绝缘垫片形成在导电结构的上侧壁上。 形成覆盖导电结构的绝缘中间层。 导电结构之间的绝缘中间层的一部分被蚀刻以形成接触孔。 接触孔的上部大于其下部。 接触孔的上部具有沿着第一方向的第一宽度和沿着平行于基底并基本上垂直于第一方向的第二方向的第二宽度。 第一宽度基本上大于第二宽度。 接触孔填充有导电材料以形成接触塞。