公开(公告)号：US08278184B1

公开(公告)日：2012-10-02

申请号：US13287131

申请日：2011-11-02

Applicant: Ying-Tsung Chen ,  Chien-Ting Lin ,  Shih-Hung Tsai ,  Ssu-I Fu ,  Wen-Tai Chiang

Inventor： Ying-Tsung Chen ,  Chien-Ting Lin ,  Shih-Hung Tsai ,  Ssu-I Fu ,  Wen-Tai Chiang

IPC: H01L21/76

CPC classification number: H01L21/324 ,  H01L21/76224 ,  H01L21/823431

Abstract: A method of forming a non-planar transistor is provided. A substrate is provided. The substrate has a plurality of isolation regions to be formed and a plurality of fin regions to be formed. A first etching process is performed to form a plurality of first trenches having a first depth in the substrate within the isolation regions. At least a doping region is formed in the substrate within the fin regions. A second etching process is performed to deepen the first depth to a second depth and a plurality of fin structures are formed in the substrate within the fin regions. Lastly, a gate is formed on the fin structures.

Abstract translation: 提供了一种形成非平面晶体管的方法。 提供基板。 基板具有要形成的多个隔离区域和要形成的多个翅片区域。 执行第一蚀刻工艺以形成在隔离区域内的衬底中具有第一深度的多个第一沟槽。 至少在鳍片区域内的衬底中形成掺杂区域。 执行第二蚀刻处理以将第一深度加深到第二深度，并且在鳍片区域内的衬底中形成多个鳍结构。 最后，在翅片结构上形成一个浇口。

公开(公告)号：US20120142157A1

公开(公告)日：2012-06-07

申请号：US12961518

申请日：2010-12-07

Applicant: Cheng-Guo Chen ,  Zhi-Cheng Lee ,  Shao-Hua Hsu ,  Jung-Tsung Tseng ,  Chien-Ting Lin ,  Cheng-Hsien Chou

Inventor： Cheng-Guo Chen ,  Zhi-Cheng Lee ,  Shao-Hua Hsu ,  Jung-Tsung Tseng ,  Chien-Ting Lin ,  Cheng-Hsien Chou

IPC: H01L21/336 ,  H01L21/302

CPC classification number: H01L21/31053 ,  H01L29/66545

Abstract: The method of fabricating a semiconductor structure according to the present invention includes planarizing an inter-layer dielectric layer and further a hard mask to remove a portion of hard mask in a thickness direction. The remaining hard mask has a thickness less than the original thickness of the hard mask. The remaining hard mask and the dummy gate are removed to form a recess. After a gate material is filled into the recess, a gate with a relatively accurate height can be obtained.

Abstract translation: 根据本发明的制造半导体结构的方法包括平面化层间电介质层和硬掩模以在厚度方向上去除一部分硬掩模。 剩余的硬掩模的厚度小于硬掩模的原始厚度。 剩余的硬掩模和伪栅被去除以形成凹部。 在栅极材料填充到凹部中之后，可以获得具有相对精确的高度的栅极。

公开(公告)号：US20110014773A1

公开(公告)日：2011-01-20

申请号：US12890725

申请日：2010-09-27

Applicant: Chien-Ting Lin ,  Che-Hua Hsu ,  Li-Wei Cheng

Inventor： Chien-Ting Lin ,  Che-Hua Hsu ,  Li-Wei Cheng

IPC: H01L21/28 ,  H01L21/762

CPC classification number: H01L21/28123 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: A method of fabricating a metal gate structure is provided. The method includes providing a semiconductor substrate with a planarized polysilicon material; patterned the planarized polysilicon material to form at least a first gate and a second gate, wherein the first gate is located on the active region and the second gate at least partially overlaps with the isolation region; forming an inter-layer dielectric material covering the gates; planarizing the inter-layer dielectric material until exposing the gates and forming an inter layer-dielectric layer; performing an etching process to remove the gates to form a first recess and a second recess within the inter-layer dielectric layer; forming a gate dielectric material on a surface of each of the recesses; forming at least a metal material within the recesses; and performing a planarization process.

Abstract translation: 提供一种制造金属栅极结构的方法。 该方法包括：提供具有平坦化多晶硅材料的半导体衬底; 将平坦化的多晶硅材料图案化以形成至少第一栅极和第二栅极，其中第一栅极位于有源区上，而第二栅极至少部分地与隔离区重叠; 形成覆盖所述栅极的层间电介质材料; 平面化层间电介质材料，直到露出栅极并形成层间介电层; 执行蚀刻工艺以移除所述栅极以在所述层间电介质层内形成第一凹部和第二凹部; 在每个所述凹部的表面上形成栅极电介质材料; 在所述凹部内形成至少一种金属材料; 并执行平面化处理。

公开(公告)号：US20100320544A1

公开(公告)日：2010-12-23

申请号：US12488592

申请日：2009-06-22

Applicant: Chih-Yu Tseng ,  Chien-Ting Lin ,  Kun-Szu Tseng ,  Cheng-Wen Fan ,  Victor-Chiang Liang

Inventor： Chih-Yu Tseng ,  Chien-Ting Lin ,  Kun-Szu Tseng ,  Cheng-Wen Fan ,  Victor-Chiang Liang

IPC: H01L27/06 ,  H01L21/02 ,  H01L21/77

CPC classification number: H01L27/0629 ,  H01L21/84 ,  H01L28/20

Abstract: A method for fabricating metal gate transistor and resistor is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation in the substrate of the resistor region; forming a tank in the shallow trench isolation of the resistor region; forming at least one gate in the transistor region and a resistor in the tank of the resistor region; and transforming the gate into a metal gate transistor.

Abstract translation: 公开了一种用于制造金属栅极晶体管和电阻器的方法。 该方法包括以下步骤：提供具有晶体管区域和电阻器区域的衬底; 在电阻器区域的衬底中形成浅沟槽隔离; 在电阻区域的浅沟槽隔离中形成一个槽; 在所述晶体管区域中形成至少一个栅极和在所述电阻器区域的所述槽中形成电阻器; 并将栅极变换为金属栅极晶体管。

公开(公告)号：US07799630B2

公开(公告)日：2010-09-21

申请号：US12018214

申请日：2008-01-23

Applicant: Chih-Hao Yu ,  Li-Wei Cheng ,  Tian-Fu Chiang ,  Cheng-Hsien Chou ,  Chien-Ting Lin ,  Che-Hua Hsu ,  Guang-Hwa Ma

Inventor： Chih-Hao Yu ,  Li-Wei Cheng ,  Tian-Fu Chiang ,  Cheng-Hsien Chou ,  Chien-Ting Lin ,  Che-Hua Hsu ,  Guang-Hwa Ma

IPC: H01L21/8238

CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7833

Abstract: A method for manufacturing a CMOS device having dual metal gate includes providing a substrate having at least two transistors of different conductive types and a dielectric layer covering the two transistors, planarizing the dielectric layer to expose gate conductive layers of the two transistors, forming a patterned blocking layer exposing one of the conductive type transistor, performing a first etching process to remove a portion of a gate of the conductive type transistor, reforming a metal gate, removing the patterned blocking layer, performing a second etching process to remove a portion of a gate of the other conductive type transistor, and reforming a metal gate.

Abstract translation: 一种用于制造具有双金属栅极的CMOS器件的方法包括：提供具有不同导电类型的至少两个晶体管的衬底和覆盖两个晶体管的电介质层，平坦化介电层以暴露两个晶体管的栅极导电层，形成图案化 阻挡层暴露导电型晶体管之一，执行第一蚀刻工艺以去除导电型晶体管的栅极的一部分，重整金属栅极，去除图案化阻挡层，执行第二蚀刻工艺以去除部分 另一导电型晶体管的栅极，以及金属栅极的重整。

公开(公告)号：US07682932B2

公开(公告)日：2010-03-23

申请号：US12126933

申请日：2008-05-26

Applicant: Chien-Ting Lin ,  Che-Hua Hsu ,  Yao-Tsung Huang ,  Guang-Hwa Ma

Inventor： Chien-Ting Lin ,  Che-Hua Hsu ,  Yao-Tsung Huang ,  Guang-Hwa Ma

IPC: H01L21/30

CPC classification number: H01L21/02694 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/02658 ,  H01L21/02667 ,  H01L21/187 ,  H01L21/2007 ,  H01L21/823807 ,  H01L29/7843

Abstract: A method for fabricating a hybrid orientation substrate includes steps of providing a direct silicon bonding (DSB) wafer having a first substrate with (100) crystalline orientation and a second substrate with (110) crystalline orientation directly bonded on the first substrate, forming and patterning a first blocking layer on the second substrate to define a first region not covered by the first blocking layer and a second region covered by the first blocking layer, performing an amorphization process to transform the first region of the second substrate into an amorphized region, and performing an annealing process to recrystallize the amorphized region into the orientation of the first substrate and to make the second region stressed by the first blocking layer.

Abstract translation: 一种用于制造混合取向衬底的方法包括以下步骤：提供具有（100）结晶取向的第一衬底的直接硅键合（DSB）晶片和具有（110）结晶取向直接接合在第一衬底上的第二衬底，形成和图案化 在第二衬底上的第一阻挡层，以限定未被第一阻挡层覆盖的第一区域和由第一阻挡层覆盖的第二区域，执行非晶化过程以将第二衬底的第一区域变换为非晶化区域;以及 执行退火处理以使非晶化区域再结晶成第一衬底的取向并使第二区域受到第一阻挡层的应力。

公开(公告)号：US20100059833A1

公开(公告)日：2010-03-11

申请号：US12208352

申请日：2008-09-11

Applicant: Chih-Hao Yu ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Cheng-Hsien Chou ,  Tian-Fu Chiang ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Jung-Tsung Tseng ,  Chien-Ting Lin ,  Guang-Hwa Ma

Inventor： Chih-Hao Yu ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Cheng-Hsien Chou ,  Tian-Fu Chiang ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Jung-Tsung Tseng ,  Chien-Ting Lin ,  Guang-Hwa Ma

IPC: H01L47/00 ,  H01L21/8236

CPC classification number: H01L29/6656 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/165 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method for fabricating metal gate transistor is disclosed. First, a substrate having a first transistor region and a second transistor region is provided. Next, a stacked film is formed on the substrate, in which the stacked film includes at least one high-k dielectric layer and a first metal layer. The stacked film is patterned to form a plurality of gates in the first transistor region and the second transistor region, a dielectric layer is formed on the gates, and a portion of the dielectric layer is planarized until reaching the top of each gates. The first metal layer is removed from the gate of the second transistor region, and a second metal layer is formed over the surface of the dielectric layer and each gate for forming a plurality of metal gates in the first transistor region and the second transistor region.

Abstract translation: 公开了一种用于制造金属栅极晶体管的方法。 首先，提供具有第一晶体管区域和第二晶体管区域的衬底。 接下来，在基板上形成层叠膜，其中层叠膜包括至少一个高k电介质层和第一金属层。 图案化层叠的膜以在第一晶体管区域和第二晶体管区域中形成多个栅极，在栅极上形成电介质层，并且介电层的一部分被平坦化，直到到达每个栅极的顶部。 第一金属层从第二晶体管区域的栅极去除，并且第二金属层形成在电介质层的表面上，每个栅极用于在第一晶体管区域和第二晶体管区域中形成多个金属栅极。

公开(公告)号：US20090242997A1

公开(公告)日：2009-10-01

申请号：US12058208

申请日：2008-03-28

Applicant: Chih-Hao Yu ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Tian-Fu Chiang ,  Cheng-Hsien Chou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Chien-Ting Lin ,  Guang-Hwa Ma

Inventor： Chih-Hao Yu ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Tian-Fu Chiang ,  Cheng-Hsien Chou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Chien-Ting Lin ,  Guang-Hwa Ma

IPC: H01L29/00 ,  H01L21/20

CPC classification number: H01L27/11

Abstract: A method for fabricating a semiconductor structure is disclosed. A substrate with a first transistor having a first dummy gate and a second transistor having a second dummy gate is provided. The conductive types of the first transistor and the second transistor are different. The first and second dummy gates are simultaneously removed to form respective first and second openings. A high-k dielectric layer, a second type conductive layer and a first low resistance conductive layer are formed on the substrate and fill in the first and second openings, with the first low resistance conductive layer filling up the second opening. The first low resistance conductive layer and the second type conductive layer in the first opening are removed. A first type conductive layer and a second low resistance conductive layer are then formed in the first opening, with the second low resistance conductive layer filling up the first opening.

Abstract translation: 公开了一种制造半导体结构的方法。 提供具有第一晶体管的衬底，其具有第一虚拟栅极和具有第二虚拟栅极的第二晶体管。 第一晶体管和第二晶体管的导电类型不同。 同时去除第一和第二伪栅极以形成相应的第一和第二开口。 在基板上形成高k电介质层，第二导电层和第一低电阻导电层，并填充第一和第二开口，第一低电阻导电层填充第二开口。 第一开口中的第一低电阻导电层和第二导电层被去除。 然后在第一开口中形成第一导电层和第二低电阻导电层，第二低电阻导电层填满第一开口。

公开(公告)号：US20080254604A1

公开(公告)日：2008-10-16

申请号：US12126933

申请日：2008-05-26

Applicant: Chien-Ting Lin ,  Che-Hua Hsu ,  Yao-Tsung Huang ,  Guang-Hwa Ma

Inventor： Chien-Ting Lin ,  Che-Hua Hsu ,  Yao-Tsung Huang ,  Guang-Hwa Ma

IPC: H01L21/265

CPC classification number: H01L21/02694 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/02658 ,  H01L21/02667 ,  H01L21/187 ,  H01L21/2007 ,  H01L21/823807 ,  H01L29/7843

Abstract: A method for fabricating a hybrid orientation substrate includes steps of providing a direct silicon bonding (DSB) wafer having a first substrate with (100) crystalline orientation and a second substrate with (110) crystalline orientation directly bonded on the first substrate, forming and patterning a first blocking layer on the second substrate to define a first region not covered by the first blocking layer and a second region covered by the first blocking layer, performing an amorphization process to transform the first region of the second substrate into an amorphized region, and performing an annealing process to recrystallize the amorphized region into the orientation of the first substrate and to make the second region stressed by the first blocking layer.

Abstract translation: 一种用于制造混合取向衬底的方法包括以下步骤：提供具有（100）结晶取向的第一衬底的直接硅键合（DSB）晶片和具有（110）结晶取向直接接合在第一衬底上的第二衬底，形成和图案化 在第二衬底上的第一阻挡层，以限定未被第一阻挡层覆盖的第一区域和由第一阻挡层覆盖的第二区域，执行非晶化过程以将第二衬底的第一区域变换为非晶化区域;以及 执行退火处理以使非晶化区域再结晶成第一衬底的取向并使第二区域受到第一阻挡层的应力。

公开(公告)号：US20070298573A1

公开(公告)日：2007-12-27

申请号：US11309094

申请日：2006-06-22

Applicant: Chien-Ting Lin ,  Liang-Wei Chen ,  Che-Hua Hsu ,  Guan-Hua Ma

Inventor： Chien-Ting Lin ,  Liang-Wei Chen ,  Che-Hua Hsu ,  Guan-Hua Ma

IPC: H01L21/336 ,  H01L21/4763

CPC classification number: H01L29/665 ,  H01L21/28097 ,  H01L29/4975 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833

Abstract: The invention is directed to a method for manufacturing a semiconductor device. The method comprises steps of forming a gate dielectric layer, a polysilicon layer and a patterned cap layer over a substrate sequentially and patterning the polysilicon layer to be a polysilicon gate by using the patterned cap layer as a mask. A plurality of lightly doped drain (LDD) regions are formed in the substrate aside the polysilicon gate, wherein a channel region is formed between the LDD regions in the substrate. A spacer is formed on the sidewall of the polysilicon gate and a source/drain region is formed in the substrate adjacent to the spacer. The patterned cap layer is removed and the spacer is removed. A metal silicidation process is performed for transforming the polysilicon gate into a metal silicide gate and forming a metal silicide layer at a surface of the source/drain region.

Abstract translation: 本发明涉及一种制造半导体器件的方法。 该方法包括以下步骤：顺序地在衬底上形成栅极电介质层，多晶硅层和图案化覆盖层，并通过使用图案化盖层作为掩模将多晶硅层图案化为多晶硅栅极。 在多晶硅栅极之外的衬底中形成多个轻掺杂漏极（LDD）区域，其中在衬底中的LDD区域之间形成沟道区域。 在多晶硅栅极的侧壁上形成间隔物，并且在与衬垫相邻的衬底中形成源/漏区。 去除图案化的盖层并移除间隔物。 进行金属硅化处理，以将多晶硅栅极变换为金属硅化物栅极，并在源极/漏极区域的表面形成金属硅化物层。