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    Semiconductor device having metal gate and manufacturing method thereof
    1.
    发明授权
    Semiconductor device having metal gate and manufacturing method thereof 有权
    具有金属栅极的半导体器件及其制造方法

    公开(公告)号：US08564063B2

    公开(公告)日：2013-10-22

    申请号：US12962624

    申请日：2010-12-07

    申请人： Ssu-I Fu ,  I-Ming Tseng ,  En-Chiuan Liou ,  Cheng-Guo Chen

    发明人： Ssu-I Fu ,  I-Ming Tseng ,  En-Chiuan Liou ,  Cheng-Guo Chen

    IPC分类号： H01L29/78

    CPC分类号： H01L29/66492 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

    摘要： A method of manufacturing a semiconductor device having metal gate includes providing a substrate having at least a dummy gate, a sacrificial layer covering sidewalls of the dummy gate and a dielectric layer exposing a top of the dummy gate formed thereon, forming a sacrificial layer covering sidewalls of the dummy gate on the substrate, forming a dielectric layer exposing a top of the dummy gate on the substrate, performing a first etching process to remove a portion of the sacrificial layer surrounding the top of the dummy gate to form at least a first recess, and performing a second etching process to remove the dummy gate to form a second recess. The first recess and the second recess construct a T-shaped gate trench.

    摘要翻译： 制造具有金属栅极的半导体器件的方法包括提供至少具有虚拟栅极的基板，覆盖伪栅极的侧壁的牺牲层和暴露其上形成的伪栅极顶部的电介质层，形成覆盖侧壁的牺牲层 形成在基板上暴露伪栅极的顶部的电介质层，执行第一蚀刻工艺以去除围绕虚拟栅极顶部的牺牲层的一部分，以形成至少第一凹部 ，并执行第二蚀刻处理以去除伪栅极以形成第二凹部。 第一凹部和第二凹部构成T形栅极沟槽。

    Method of selectively removing patterned hard mask
    2.
    发明授权
    Method of selectively removing patterned hard mask 有权
    选择性去除图案化硬掩模的方法

    公开(公告)号：US08486842B2

    公开(公告)日：2013-07-16

    申请号：US12901453

    申请日：2010-10-08

    申请人： Che-Hua Hsu ,  Shao-Hua Hsu ,  Zhi-Cheng Lee ,  Cheng-Guo Chen

    发明人： Che-Hua Hsu ,  Shao-Hua Hsu ,  Zhi-Cheng Lee ,  Cheng-Guo Chen

    IPC分类号： H01L21/302

    CPC分类号： H01L21/31144 ,  H01L27/0629 ,  H01L28/24

    摘要： A method of selectively removing a patterned hard mask is described. A substrate with a patterned target layer thereon is provided, wherein the patterned target layer includes a first target pattern and at least one second target pattern, and the patterned hard mask includes a first mask pattern on the first target pattern and a second mask pattern on the at least one second target pattern. A first photoresist layer is formed covering the first mask pattern. The sidewall of the at least one second target pattern is covered by a second photoresist layer. The second mask pattern is removed using the first photoresist layer and the second photoresist layer as a mask.

    摘要翻译： 描述了选择性地去除图案化的硬掩模的方法。 提供了其上具有图案化目标层的衬底，其中所述图案化目标层包括第一目标图案和至少一个第二目标图案，并且所述图案化硬掩模包括第一目标图案上的第一掩模图案和第二掩模图案 所述至少一个第二目标图案。 形成覆盖第一掩模图案的第一光致抗蚀剂层。 所述至少一个第二目标图案的侧壁被第二光致抗蚀剂层覆盖。 使用第一光致抗蚀剂层和第二光致抗蚀剂层作为掩模去除第二掩模图案。

    SEMICONDUCTOR DEVICE HAVING METAL GATE AND MANUFACTURING METHOD THEREOF
    5.
    发明申请
    SEMICONDUCTOR DEVICE HAVING METAL GATE AND MANUFACTURING METHOD THEREOF 有权
    具有金属门的半导体器件及其制造方法

    公开(公告)号：US20120139042A1

    公开(公告)日：2012-06-07

    申请号：US12962624

    申请日：2010-12-07

    申请人： Ssu-I Fu ,  I-Ming Tseng ,  En-Chiuan Liou ,  Cheng-Guo Chen

    发明人： Ssu-I Fu ,  I-Ming Tseng ,  En-Chiuan Liou ,  Cheng-Guo Chen

    IPC分类号： H01L21/336 ,  H01L29/78

    CPC分类号： H01L29/66492 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

    摘要： A method of manufacturing a semiconductor device having metal gate includes providing a substrate having at least a dummy gate, a sacrificial layer covering sidewalls of the dummy gate and a dielectric layer exposing a top of the dummy gate formed thereon, forming a sacrificial layer covering sidewalls of the dummy gate on the substrate, forming a dielectric layer exposing a top of the dummy gate on the substrate, performing a first etching process to remove a portion of the sacrificial layer surrounding the top of the dummy gate to form at least a first recess, and performing a second etching process to remove the dummy gate to form a second recess. The first recess and the second recess construct a T-shaped gate trench.

    摘要翻译： 制造具有金属栅极的半导体器件的方法包括提供至少具有虚拟栅极的基板，覆盖伪栅极的侧壁的牺牲层和暴露其上形成的伪栅极顶部的电介质层，形成覆盖侧壁的牺牲层 形成在基板上暴露伪栅极的顶部的电介质层，执行第一蚀刻工艺以去除围绕虚拟栅极顶部的牺牲层的一部分，以形成至少第一凹部 ，并执行第二蚀刻处理以去除伪栅极以形成第二凹部。 第一凹部和第二凹部构成T形栅极沟槽。

    Method of fabricating efuse structure, resistor sturcture and transistor sturcture
    8.
    发明授权
    Method of fabricating efuse structure, resistor sturcture and transistor sturcture 有权
    制造efuse结构，电阻结构和晶体管结构的方法

    公开(公告)号：US08003461B1

    公开(公告)日：2011-08-23

    申请号：US12700707

    申请日：2010-02-04

    申请人： Che-Hua Hsu ,  Zhi-Cheng Lee ,  Cheng-Guo Chen ,  Shao-Hua Hsu

    发明人： Che-Hua Hsu ,  Zhi-Cheng Lee ,  Cheng-Guo Chen ,  Shao-Hua Hsu

    IPC分类号： H01L21/8242

    CPC分类号： H01L21/02 ,  H01L21/8234

    摘要： A method of fabricating an efuse structure, a resistor structure and a transistor structure. First, a work function metal layer, a polysilicon layer and a first hard mask layer are formed to cover a transistor region, a resistor region and an e-fuse region on a substrate. Then, the work function metal layer on the resistor region and the efuse region is removed by using a first photomask. Later, a gate, a resistor, an efuse are formed in the transistor region, the resistor region and the efuse region respectively. After that, a dielectric layer aligning with the top surface of the gate is formed. Later, the polysilicon layer in the gate is removed by taking a second hard mask as a mask to form a recess. Finally, a metal layer fills up the recess.

    摘要翻译： 一种制造efuse结构，电阻器结构和晶体管结构的方法。 首先，形成工作功能金属层，多晶硅层和第一硬掩模层，以覆盖基板上的晶体管区域，电阻区域和e熔丝区域。 然后，通过使用第一光掩模去除电阻器区域和efuse区域上的功函数金属层。 之后，在晶体管区域，电阻区域和efuse区域分别形成栅极，电阻器，efuse。 之后，形成与栅极顶表面对准的电介质层。 之后，通过取第二硬掩模作为掩模来除去栅极中的多晶硅层以形成凹陷。 最后，金属层填满凹槽。

    METHOD OF FABRICATING EFUSE STRUCTURE, RESISTOR STURCTURE AND TRANSISTOR STURCTURE
    9.
    发明申请
    METHOD OF FABRICATING EFUSE STRUCTURE, RESISTOR STURCTURE AND TRANSISTOR STURCTURE 有权
    制作EFUSE结构，电阻器和晶体管的方法

    公开(公告)号：US20110189827A1

    公开(公告)日：2011-08-04

    申请号：US12700707

    申请日：2010-02-04

    申请人： Che-Hua Hsu ,  Zhi-Cheng Lee ,  Cheng-Guo Chen ,  Shao-Hua Hsu

    发明人： Che-Hua Hsu ,  Zhi-Cheng Lee ,  Cheng-Guo Chen ,  Shao-Hua Hsu

    IPC分类号： H01L21/8234 ,  H01L21/02

    CPC分类号： H01L21/02 ,  H01L21/8234

    摘要： A method of fabricating an efuse structure, a resistor structure and a transistor structure. First, a work function metal layer, a polysilicon layer and a first hard mask layer are formed to cover a transistor region, a resistor region and an e-fuse region on a substrate. Then, the work function metal layer on the resistor region and the efuse region is removed by using a first photomask. Later, a gate, a resistor, an efuse are formed in the transistor region, the resistor region and the efuse region respectively. After that, a dielectric layer aligning with the top surface of the gate is formed. Later, the polysilicon layer in the gate is removed by taking a second hard mask as a mask to form a recess. Finally, a metal layer fills up the recess.

    摘要翻译： 一种制造efuse结构，电阻器结构和晶体管结构的方法。 首先，形成工作功能金属层，多晶硅层和第一硬掩模层，以覆盖基板上的晶体管区域，电阻区域和e熔丝区域。 然后，通过使用第一光掩模去除电阻器区域和efuse区域上的功函数金属层。 之后，在晶体管区域，电阻区域和efuse区域分别形成栅极，电阻器，efuse。 之后，形成与栅极顶表面对准的电介质层。 之后，通过取第二硬掩模作为掩模来除去栅极中的多晶硅层以形成凹陷。 最后，金属层填满凹槽。