公开(公告)号：US20080072029A1

公开(公告)日：2008-03-20

申请号：US11985149

申请日：2007-11-13

Applicant: Ling-Hung Yu ,  Ying-Chih Lu ,  Chun-Yi Lee ,  Chi-Tsung Chang ,  Meng-Hua Cheng ,  Chun-Lung Wu

Inventor： Ling-Hung Yu ,  Ying-Chih Lu ,  Chun-Yi Lee ,  Chi-Tsung Chang ,  Meng-Hua Cheng ,  Chun-Lung Wu

IPC: G06F15/177

CPC classification number: G06F9/4401 ,  G06F15/177

Abstract: A method for executing the power on self test (POST) on the computer system and a method for updating the SMBIOS information partially are provided for a computer system with a first memory and a second memory, wherein the first memory comprises a first storage block and a second storage block. A user can previously set the specific SMBIOS information in the second storage block. And during the POST stage, the default SMBIOS information in the BIOS code loaded from the first storage block to the second memory will be partially updated according to the specific SMBIOS information set by the user. As a result, the purpose of using the appropriated SMBIOS information to initiate the computer system can be achieved.

Abstract translation: 一种用于在计算机系统上执行电源自检（POST）的方法和部分地用于更新SMBIOS信息的方法被提供给具有第一存储器和第二存储器的计算机系统，其中第一存储器包括第一存储块和 第二个存储块。 用户可以预先在第二个存储块中设置特定的SMBIOS信息。 在POST阶段，从第一个存储块加载到第二个存储器的BIOS代码中的默认SMBIOS信息将根据用户设置的特定SMBIOS信息进行部分更新。 因此，可以实现使用专用的SMBIOS信息来启动计算机系统的目的。

公开(公告)号：US20080005434A1

公开(公告)日：2008-01-03

申请号：US11748984

申请日：2007-05-15

Applicant: Chun-Yi Lee ,  Kuen-Long Chang ,  Chun-Hsiung Hung ,  Yu-Lan Kuo

Inventor： Chun-Yi Lee ,  Kuen-Long Chang ,  Chun-Hsiung Hung ,  Yu-Lan Kuo

IPC: G06F13/00

CPC classification number: G06F13/4291

Abstract: Various embodiments increase the speed of communication over a multi-mode bus by communicating data over multiple pins in the same direction. The bus includes multiple data communication pins communicating over the bus. The bus includes a chip select pin indicating whether communication is occurring between the integrated circuit and another integrated circuit. The bus includes a clock pin. The bus includes a mode control circuit. In one mode, two of the data communication pins communicate in opposite directions between the integrated circuit and another integrated circuit. In another mode, two of the data communication pins communicate in a same direction between the integrated circuit and another integrated circuit. In some embodiments, the bus follows a Serial Peripheral Interface standard. In various embodiments, data is communicated from the integrated circuit to another integrated circuit, or from another integrated circuit to the integrated circuit.

Abstract translation: 各种实施例通过在相同方向上在多个引脚上传送数据来增加多模总线上的通信速度。 总线包括通过总线通信的多个数据通信引脚。 总线包括芯片选择引脚，指示集成电路和另一集成电路之间是否发生通信。 总线包括一个时钟引脚。 总线包括模式控制电路。 在一种模式中，两个数据通信引脚在集成电路和另一个集成电路之间的相反方向上通信。 在另一种模式中，两个数据通信引脚在集成电路和另一个集成电路之间沿相同的方向通信。 在一些实施例中，总线遵循串行外设接口标准。 在各种实施例中，数据从集成电路传送到另一集成电路，或从另一集成电路传送到集成电路。

公开(公告)号：US20060224874A1

公开(公告)日：2006-10-05

申请号：US11095782

申请日：2005-03-30

Applicant: Ying-Chih Lu ,  Chun-Lung Wu ,  Chun-Yi Lee ,  Lung-Hung Yu ,  Chi-Tsung Chang ,  Meng-Hua Cheng

Inventor： Ying-Chih Lu ,  Chun-Lung Wu ,  Chun-Yi Lee ,  Lung-Hung Yu ,  Chi-Tsung Chang ,  Meng-Hua Cheng

IPC: G06F9/445

CPC classification number: G06F9/4401

Abstract: A method for updating System Management Basic Input Output System (SMBIOS) data in BIOS of a computer system is provided so as to allow a user to store user-defined information in a storage unit of a computer system, wherein the storage unit has a default SMBIOS data. This method establishes an accessing block in the BIOS that enable the user to access user data, determines whether the accessing block contains the user data after activating the BIOS. If there is user data in the accessing block, the user data is stored in the storage unit and the default SMBIOS data is removed; otherwise, the default SMBIOS data is retained, thereby achieving the advantage of easy update.

Abstract translation: 提供了一种用于在计算机系统的BIOS中更新系统管理基本输入输出系统（SMBIOS）数据的方法，以允许用户将用户定义的信息存储在计算机系统的存储单元中，其中存储单元具有默认 SMBIOS数据。 该方法在BIOS中建立一个访问块，使用户能够访问用户数据，确定访问块是否在激活BIOS后包含用户数据。 如果访问块中存在用户数据，则将用户数据存储在存储单元中，并删除默认的SMBIOS数据; 否则，保留默认SMBIOS数据，从而实现易于更新的优点。

公开(公告)号：US20060178785A1

公开(公告)日：2006-08-10

申请号：US11053571

申请日：2005-02-07

Applicant: Chi-Tsung Chang ,  Ying-Chih Lu ,  Meng-Hua Cheng ,  Chun-Yi Lee ,  Ling-Hung Yu ,  Chia-Hsing Lee

Inventor： Chi-Tsung Chang ,  Ying-Chih Lu ,  Meng-Hua Cheng ,  Chun-Yi Lee ,  Ling-Hung Yu ,  Chia-Hsing Lee

IPC: G05D23/00

CPC classification number: G05D23/1917

Abstract: A heat dissipating method is applied to a computer system having a timing signaling mechanism and a temperature sensing unit. Firstly, a process of setting a dissipating temperature operating mode is performed. Then, a periodic signal is regularly transmitted to a basic input output system by the timing signaling mechanism of the computer system, and a temperature of each of hardware devices is regularly sensed by the temperature sensing unit. Subsequently, a heat dissipating unit of each of the hardware devices is actuated to perform a heat dissipation process according to the temperature sensed by the temperature sensing unit and the dissipating temperature operating mode. Therefore, the present invention can control operating intensity of the heat dissipating units and achieve hardware monitoring without requiring additional software or hardware, such that heat dissipating and operation efficiencies of the hardware devices of the computer system can be improved.

Abstract translation: 散热方法应用于具有定时信令机构和温度感测单元的计算机系统。 首先，进行设定耗散温度运转模式的处理。 然后，通过计算机系统的定时信令机制将周期性信号定期地发送到基本输入输出系统，并且由温度感测单元定期地感测每个硬件设备的温度。 随后，驱动每个硬件装置的散热单元，以根据由温度检测单元感测的温度和散热温度运行模式进行散热处理。 因此，本发明可以控制散热单元的操作强度，并且实现硬件监视而不需要额外的软件或硬件，从而可以提高计算机系统的硬件设备的散热和运行效率。

公开(公告)号：US08786025B2

公开(公告)日：2014-07-22

申请号：US13451261

申请日：2012-04-19

Applicant: Jui-Yao Lai ,  Chun-Yi Lee ,  Shyh-Wei Wang ,  Yen-Ming Chen

Inventor： Jui-Yao Lai ,  Chun-Yi Lee ,  Shyh-Wei Wang ,  Yen-Ming Chen

IPC: H01L21/70

CPC classification number: H01L28/24 ,  H01L21/823842 ,  H01L23/5228 ,  H01L27/0629 ,  H01L27/0802 ,  H01L28/20 ,  H01L29/0649 ,  H01L29/0847 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A system and method for forming a resistor system is provided. An embodiment comprises a resistor formed in a U-shape. The resistor may comprise multiple layers of conductive materials, with a dielectric layer filling the remainder of the U-shape. The resistor may be integrated with a dual metal gate manufacturing process or may be integrated with multiple types of resistors.

Abstract translation: 提供一种用于形成电阻系统的系统和方法。 实施例包括形成为U形的电阻器。 电阻器可以包括多层导电材料，其中介电层填充U形的其余部分。 电阻器可以与双金属栅极制造工艺集成，或者可以与多种类型的电阻器集成。

公开(公告)号：US20130279265A1

公开(公告)日：2013-10-24

申请号：US13453312

申请日：2012-04-23

Applicant: Chun-Yi Lee ,  Kuen-Long Chang ,  Chun-Hsiung Hung

Inventor： Chun-Yi Lee ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC: G11C16/04

CPC classification number: G11C16/14 ,  G11C16/16 ,  G11C16/344

Abstract: Memory cells of a nonvolatile memory array are characterized by one of multiple threshold voltage ranges including at least an erased threshold voltage range and a programmed threshold voltage range. Responsive to an erase command to erase a group of memory cells of the nonvolatile memory array, a plurality of phases are performed, including at least a pre-program phase and an erase phase. The pre-program phase programs a first set of memory cells in the group having threshold voltages within the erased threshold voltage range, and does not program a second set of memory cells in the group having threshold voltages within the erased threshold voltage range in the group. By not programming the second set of memory cells, the pre-program phase is performed more quickly than if the second set of memory cells were programmed along with the first set of memory cells.

Abstract translation: 非易失性存储器阵列的存储单元的特征在于包括至少一个擦除的阈值电压范围和编程的阈值电压范围的多个阈值电压范围之一。 响应于擦除非易失性存储器阵列的一组存储单元的擦除命令，执行至少包括预编程相位和擦除阶段的多个相位。 预编程相位对组内的阈值电压中的第一组存储器单元进行编程，并且不对组中擦除的阈值电压范围内的阈值电压的组中的第二组存储器单元进行编程 。 通过不对第二组存储器单元进行编程，如果第二组存储器单元与第一组存储器单元一起被编程，那么执行预编程相位更快。

公开(公告)号：US20130181191A1

公开(公告)日：2013-07-18

申请号：US13485968

申请日：2012-06-01

Applicant: Jenn-Chang Hwang ,  Chao-Ying Hsieh ,  Lung-Kai Mao ,  Chun-Yi Lee ,  Li-Shiuan Tsai ,  Cheng-Lung Tsai ,  Wei-Cheng Chung ,  Ping-Chiang Lyu

Inventor： Jenn-Chang Hwang ,  Chao-Ying Hsieh ,  Lung-Kai Mao ,  Chun-Yi Lee ,  Li-Shiuan Tsai ,  Cheng-Lung Tsai ,  Wei-Cheng Chung ,  Ping-Chiang Lyu

IPC: H01L51/10 ,  H01L21/02

CPC classification number: H01L51/0093 ,  B82Y10/00 ,  H01L51/052 ,  H01L51/0545

Abstract: An electronic device including a bio-polymer material and a method for manufacturing the same are disclosed. The electronic device of the present invention comprises: a substrate; a first electrode disposed on the substrate; a bio-polymer layer disposed on the first electrode, wherein the bio-polymeric material is selected from a group consisting of wool keratin, collagen hydrolysate, gelatin, whey protein and hydroxypropyl methylcellulose; and a second electrode disposed on the biopolymer material layer. The present invention is suitable for various electronic devices such as an organic thin film transistor, an organic floating gate memory, or a metal-insulator-metal capacitor.

Abstract translation: 公开了一种包括生物聚合物材料的电子设备及其制造方法。 本发明的电子器件包括：衬底; 设置在所述基板上的第一电极; 设置在所述第一电极上的生物聚合物层，其中所述生物聚合物材料选自由羊毛角蛋白，胶原水解产物，明胶，乳清蛋白和羟丙基甲基纤维素组成的组; 以及设置在所述生物聚合物材料层上的第二电极。 本发明适用于有机薄膜晶体管，有机浮栅存储器或金属 - 绝缘体 - 金属电容器等各种电子器件。

公开(公告)号：US20130102138A1

公开(公告)日：2013-04-25

申请号：US13280770

申请日：2011-10-25

Applicant: Ming-Hsi YEH ,  Tsung-Chieh TSAI ,  Chun-Yi LEE

Inventor： Ming-Hsi YEH ,  Tsung-Chieh TSAI ,  Chun-Yi LEE

IPC: H01L21/28

CPC classification number: H01L21/28008 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/092

Abstract: A method for fabricating a semiconductor device is disclosed. A dummy gate feature is formed between two active gate features in an inter-layer dielectric (ILD) over a substrate. An isolation structure is in the substrate and the dummy gate feature is over the isolation structure. Source/drain (S/D) features are formed at edges of the active gate features in the substrate for forming transistor devices. The disclosed method provides an improved method for reducing parasitic capacitance among the transistor devices. In an embodiment, the improved formation method is achieved by introducing species into the dummy gate feature to increase the resistance of the dummy gate feature.

Abstract translation: 公开了一种制造半导体器件的方法。 在衬底上的层间电介质（ILD）中的两个有源栅极特征之间形成虚拟栅极特征。 隔离结构位于衬底中，虚拟栅极特征位于隔离结构之上。 源极/漏极（S / D）特征形成在用于形成晶体管器件的衬底中的有源栅极特征的边缘处。 所公开的方法提供了一种用于减小晶体管器件之间的寄生电容的改进方法。 在一个实施例中，通过将物质引入虚拟栅极特征来增加虚拟栅极特征的电阻来实现改进的形成方法。

公开(公告)号：US08411509B2

公开(公告)日：2013-04-02

申请号：US11976975

申请日：2007-10-30

Applicant: Chun-Yi Lee ,  Yung-Feng Lin ,  Kuen-Long Chang ,  Chun-Hsiung Hung

Inventor： Chun-Yi Lee ,  Yung-Feng Lin ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC: G11C11/34

CPC classification number: G11C8/08 ,  G11C8/14 ,  G11C16/08

Abstract: A memory and method for charging a word line thereof are disclosed. The memory includes a first word line driver, a first word line and a first switch. The first word line driver is connected to a first operational voltage for receiving a first control signal. The first word line comprises a start terminal connected to an output terminal of the first word line driver. The first switch is connected to a second operational voltage and an end terminal of the first word line. The second operational voltage is not smaller than the first operational voltage. When the first word line driver is controlled by the first control signal to start charging up the first word line, the first switch is simultaneously turned on to provide another charging path for the first word line until the first word line is charged to the first operational voltage.

公开(公告)号：US20120175602A1

公开(公告)日：2012-07-12

申请号：US13425284

申请日：2012-03-20

Applicant: Jenn-Chang HWANG ,  Li-Shiuan TSAI ,  Chun-Yi LEE ,  Cheng-Lun TSAI

Inventor： Jenn-Chang HWANG ,  Li-Shiuan TSAI ,  Chun-Yi LEE ,  Cheng-Lun TSAI

IPC: H01L51/10 ,  H01L51/40

CPC classification number: H01L51/0055 ,  B82Y10/00 ,  H01L28/40 ,  H01L51/0046 ,  H01L51/0053 ,  H01L51/0093 ,  H01L51/052 ,  H01L51/0545 ,  H01L51/0562

Abstract: An N-type organic thin film transistor, an ambipolar field-effect transistor, and methods of fabricating the same are disclosed. The N-type organic thin film transistor of the present invention comprises: a substrate; a gate electrode locating on the substrate; a gate-insulating layer covering the gate electrode, and the gate-insulating layer is made of silk protein; a buffering layer locating on the gate-insulating layer, and the buffering layer is made of pentacene; an N-type organic semiconductor layer locating on the buffering layer; and a source and a drain electrode, wherein the N-type organic semiconductor layer, the buffering layer, the source and the drain electrode are disposed over the gate dielectric layer.

Abstract translation: 公开了一种N型有机薄膜晶体管，双极场效应晶体管及其制造方法。 本发明的N型有机薄膜晶体管包括：基板; 位于基板上的栅电极; 覆盖栅电极的栅极绝缘层，栅绝缘层由丝蛋白制成; 位于栅极绝缘层上的缓冲层，缓冲层由并五苯制成; 位于缓冲层上的N型有机半导体层; 以及源极和漏极，其中所述N型有机半导体层，所述缓冲层，所述源极和漏极被设置在所述栅极介电层上。