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    Non-volatile semiconductor memory device with alternative metal gate material
    21.
    发明申请
    Non-volatile semiconductor memory device with alternative metal gate material 有权
    具有替代金属栅极材料的非易失性半导体存储器件

    公开(公告)号：US20060118858A1

    公开(公告)日：2006-06-08

    申请号：US11246114

    申请日：2005-10-11

    Applicant: Sang-hun Jeon ,  Jeong-hee Han ,  Chung-woo Kim

    Inventor： Sang-hun Jeon ,  Jeong-hee Han ,  Chung-woo Kim

    IPC: H01L29/788

    CPC classification number: H01L29/513 ,  G11C16/0416 ,  G11C16/0466 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/7881 ,  H01L29/792

    Abstract: A non-volatile semiconductor memory device comprises a substrate including a source region, a drain region and a channel region provided between the source region and the drain region with a gate stack located above the channel region with a metal gate located above the gate stack. The metal gate is comprised of a metal having a specific metal work function relative to a composition of a layer of the gate stack that causes electrons to travel through the entire thickness of the blocking layer via direct tunneling. The gate stack preferably comprises a multiple layer stack selected from a group of multiple layer stacks consisting of: ONO, ONH, OHH, OHO, HHH, or HNH, where O is an oxide material, N is SiN, and H is a high κ material.

    Abstract translation: 非易失性半导体存储器件包括：衬底，其包括源区域，漏极区域和设置在源极区域和漏极区域之间的沟道区域，栅极堆叠位于沟道区域上方，金属栅极位于栅极叠层之上。 金属栅极由具有特定的金属功函数的金属组成，相对于栅堆叠层的组成，其使电子通过直接隧道穿过阻挡层的整个厚度。 栅极堆叠优选地包括选自由以下组成的多层堆叠的多层堆叠：ONO，ONH，OHH，OHO，HHH或HNH，其中O是氧化物材料，N是SiN，H是高kappa 材料。

    Automatic switchover mechanism in a network device
    24.
    发明授权
    Automatic switchover mechanism in a network device 有权
    网络设备自动切换机制

    公开(公告)号：US08295169B2

    公开(公告)日：2012-10-23

    申请号：US12796170

    申请日：2010-06-08

    Applicant: Hsien-Chung Woo

    Inventor： Hsien-Chung Woo

    IPC: H04L1/00 ,  H04L12/26 ,  H04L12/28

    CPC classification number: H04L1/22 ,  H04L45/22 ,  H04L45/28 ,  H04L45/60

    Abstract: A system comprises a plurality of processing modules, one of which is designated to be the primary processing module and the others are designated to be secondary processing modules. During operation, state is maintained in the primary processing module and at least one of the secondary processing modules. A switchover controller causes outputs from the secondary modules to be discarded. When the switchover controller receives an indication that the primary processing module has failed, it designates one of the secondary processing modules to be the primary processing module. Because the newly designated primary processing module already has current state information at switchover, the module is able to operate with minimal delay.

    Abstract translation: 系统包括多个处理模块，其中一个处理模块被指定为主处理模块，其他处理模块被指定为二次处理模块。 在操作期间，状态保持在主处理模块和至少一个辅助处理模块中。 切换控制器使得二次模块的输出被丢弃。 当切换控制器接收到主处理模块出现故障的指示时，将其中一个辅助处理模块指定为主处理模块。 因为新指定的主处理模块在切换时已经具有当前状态信息，所以该模块能够以最小的延迟进行操作。

    Non-volatile memory device including metal-insulator transition material
    25.
    发明授权
    Non-volatile memory device including metal-insulator transition material 失效
    包括金属 - 绝缘体过渡材料的非易失性存储器件

    公开(公告)号：US08237214B2

    公开(公告)日：2012-08-07

    申请号：US11980352

    申请日：2007-10-31

    Applicant: Wan-jun Park ,  Jo-won Lee ,  Sang-hun Jeon ,  Chung-woo Kim

    Inventor： Wan-jun Park ,  Jo-won Lee ,  Sang-hun Jeon ,  Chung-woo Kim

    IPC: H01L29/792

    CPC classification number: H01L21/28273 ,  H01L21/28282

    Abstract: A non-volatile memory device including a metal-insulator transition (MIT) material is provided. The non-volatile memory device includes a gate stack having a tunneling layer, a charge trap layer, a blocking layer and a gate electrode formed on a substrate, wherein at least one of the tunneling layer and the blocking layer is formed of an MIT (metal-insulator transition) material.

    Abstract translation: 提供了包括金属 - 绝缘体转变（MIT）材料的非易失性存储器件。 非易失性存储器件包括具有隧道层，电荷陷阱层，形成在衬底上的阻挡层和栅电极的栅极堆叠，其中隧道层和阻挡层中的至少一个由MIT形成 金属 - 绝缘体转变）材料。

    Adaptive network router
    26.
    发明授权
    Adaptive network router 有权
    自适应网络路由器

    公开(公告)号：US07869352B1

    公开(公告)日：2011-01-11

    申请号：US12364912

    申请日：2009-02-03

    Applicant: Stephen W. Turner ,  Hsien-Chung Woo ,  Sanjay Kalra ,  Truman Joe ,  Wendy R. Cartee

    Inventor： Stephen W. Turner ,  Hsien-Chung Woo ,  Sanjay Kalra ,  Truman Joe ,  Wendy R. Cartee

    IPC: G06F11/00 ,  H04J3/14 ,  H04L1/00

    CPC classification number: H04L12/4633 ,  H04L45/00 ,  H04L45/38 ,  H04L63/1416 ,  H04L63/1458

    Abstract: A network router includes a set of interface cards to receive packets from a network, and a set of accounting modules to calculate flow statistics for the packets. The router further includes a control unit to adaptively update routing information in response to the calculated flow statistics, and to route the packets in accordance with the routing information. The control unit identifies potentially malicious packet flows for the received packets based on the flow statistics, and applies an intercept filter to intercept the packets of the identified packet flows. The control unit analyzes the intercepted packets in real-time to determine the presence of a network event, and updates the routing information based on the determination, e.g., by terminating routing for packets associated with malicious packet flows. In this manner, the router may adaptively respond to network events, such as network security violations.

    Abstract translation: 网络路由器包括一组用于从网络接收分组的接口卡，以及一组用于计算分组的流统计的计费模块。 路由器还包括控制单元，用于响应于所计算的流量统计自适应地更新路由信息，并且根据路由信息来路由分组。 控制单元基于流统计识别接收到的分组的潜在恶意分组流，并应用截取过滤器来截取所识别的分组流的分组。 控制单元实时地分析所拦截的分组以确定网络事件的存在，并且例如通过终止与恶意分组流相关联的分组的路由，基于确定来更新路由信息。 以这种方式，路由器可以自适应地响应诸如网络安全违规的网络事件。

    AUTOMATIC SWITCHOVER MECHANISM IN A NETWORK DEVICE
    28.
    发明申请
    AUTOMATIC SWITCHOVER MECHANISM IN A NETWORK DEVICE 有权
    网络设备自动切换机制

    公开(公告)号：US20100246392A1

    公开(公告)日：2010-09-30

    申请号：US12796170

    申请日：2010-06-08

    Applicant: Hsien-Chung WOO

    Inventor： Hsien-Chung WOO

    IPC: H04L1/00

    CPC classification number: H04L1/22 ,  H04L45/22 ,  H04L45/28 ,  H04L45/60

    Abstract: A system comprises a plurality of processing modules, one of which is designated to be the primary processing module and the others are designated to be secondary processing modules. During operation, state is maintained in the primary processing module and at least one of the secondary processing modules. A switchover controller causes outputs from the secondary modules to be discarded. When the switchover controller receives an indication that the primary processing module has failed, it designates one of the secondary processing modules to be the primary processing module. Because the newly designated primary processing module already has current state information at switchover, the module is able to operate with minimal delay.

    Abstract translation: 系统包括多个处理模块，其中一个处理模块被指定为主处理模块，其他处理模块被指定为二次处理模块。 在操作期间，状态保持在主处理模块和至少一个辅助处理模块中。 切换控制器使得二次模块的输出被丢弃。 当切换控制器接收到主处理模块出现故障的指示时，将其中一个辅助处理模块指定为主处理模块。 因为新指定的主处理模块在切换时已经具有当前状态信息，所以该模块能够以最小的延迟进行操作。

    Multi-bit non-volatile memory device, method of operating the same, and method of fabricating the same
    29.
    发明授权
    Multi-bit non-volatile memory device, method of operating the same, and method of fabricating the same 失效
    多位非易失性存储器件，其操作方法及其制造方法

    公开(公告)号：US07759196B2

    公开(公告)日：2010-07-20

    申请号：US12209735

    申请日：2008-09-12

    Applicant: Soo-doo Chae ,  Moon-kyung Kim ,  Jo-won Lee ,  Chung-woo Kim

    Inventor： Soo-doo Chae ,  Moon-kyung Kim ,  Jo-won Lee ,  Chung-woo Kim

    IPC: H01L21/336 ,  H01L29/788

    CPC classification number: G11C16/0475 ,  H01L21/28282 ,  H01L29/66833 ,  H01L29/7923

    Abstract: A multi-bit non-volatile memory device and methods of operating and fabricating the same may be provided. The memory device may include a channel region formed in a semiconductor substrate, and a source and drain that form a Schottky contact with the channel region. Also, a central gate electrode may be located on a portion of the channel region, and first and second sidewall gate electrodes may be formed on the channel region along the outer sides of the central gate electrode. First and second storage nodes may be formed between the channel region and the sidewall gate electrodes.

    Abstract translation: 可以提供多位非易失性存储器件及其操作和制造方法。 存储器件可以包括形成在半导体衬底中的沟道区，以及与沟道区形成肖特基接触的源极和漏极。 此外，中心栅电极可以位于沟道区的一部分上，并且第一和第二侧壁栅极可以沿着中心栅电极的外侧形成在沟道区上。 第一和第二存储节点可以形成在沟道区和侧壁栅电极之间。

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