公开(公告)号：US20060118858A1

公开(公告)日：2006-06-08

申请号：US11246114

申请日：2005-10-11

申请人： Sang-hun Jeon ,  Jeong-hee Han ,  Chung-woo Kim

发明人： Sang-hun Jeon ,  Jeong-hee Han ,  Chung-woo Kim

IPC分类号： H01L29/788

CPC分类号： H01L29/513 ,  G11C16/0416 ,  G11C16/0466 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/7881 ,  H01L29/792

摘要： A non-volatile semiconductor memory device comprises a substrate including a source region, a drain region and a channel region provided between the source region and the drain region with a gate stack located above the channel region with a metal gate located above the gate stack. The metal gate is comprised of a metal having a specific metal work function relative to a composition of a layer of the gate stack that causes electrons to travel through the entire thickness of the blocking layer via direct tunneling. The gate stack preferably comprises a multiple layer stack selected from a group of multiple layer stacks consisting of: ONO, ONH, OHH, OHO, HHH, or HNH, where O is an oxide material, N is SiN, and H is a high κ material.

摘要翻译： 非易失性半导体存储器件包括：衬底，其包括源区域，漏极区域和设置在源极区域和漏极区域之间的沟道区域，栅极堆叠位于沟道区域上方，金属栅极位于栅极叠层之上。 金属栅极由具有特定的金属功函数的金属组成，相对于栅堆叠层的组成，其使电子通过直接隧道穿过阻挡层的整个厚度。 栅极堆叠优选地包括选自由以下组成的多层堆叠的多层堆叠：ONO，ONH，OHH，OHO，HHH或HNH，其中O是氧化物材料，N是SiN，H是高kappa 材料。

公开(公告)号：US07391075B2

公开(公告)日：2008-06-24

申请号：US11246114

申请日：2005-10-11

申请人： Sang-hun Jeon ,  Jeong-hee Han ,  Chung-woo Kim

发明人： Sang-hun Jeon ,  Jeong-hee Han ,  Chung-woo Kim

IPC分类号： H01L29/788

CPC分类号： H01L29/513 ,  G11C16/0416 ,  G11C16/0466 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/7881 ,  H01L29/792

摘要： A non-volatile semiconductor memory device comprises a substrate including a source region, a drain region and a channel region provided between the source region and the drain region with a gate stack located above the channel region with a metal gate located above the gate stack. The metal gate is comprised of a metal having a specific metal work function relative to a composition of a layer of the gate stack that causes electrons to travel through the entire thickness of the blocking layer via direct tunneling. The gate stack preferably comprises a multiple layer stack selected from a group of multiple layer stacks consisting of: ONO, ONH, OHH, OHO, HHH, or HNH, where O is an oxide material, N is SiN, and H is a high κ material.

摘要翻译： 非易失性半导体存储器件包括：衬底，其包括源区域，漏极区域和设置在源极区域和漏极区域之间的沟道区域，栅极堆叠位于沟道区域上方，金属栅极位于栅极叠层之上。 金属栅极由具有特定的金属功函数的金属组成，相对于栅堆叠层的组成，其使电子通过直接隧道穿过阻挡层的整个厚度。 栅极堆叠优选地包括选自由以下组成的多层堆叠的多层堆叠：ONO，ONH，OHH，OHO，HHH或HNH，其中O是氧化物材料，N是SiN，H是高kappa 材料。

公开(公告)号：US07402492B2

公开(公告)日：2008-07-22

申请号：US11385642

申请日：2006-03-21

申请人： Sang-hun Jeon ,  Kyu-sik Kim ,  Chung-woo Kim ,  Sung-ho Park ,  Yo-sep Min ,  Jeong-hee Han

发明人： Sang-hun Jeon ,  Kyu-sik Kim ,  Chung-woo Kim ,  Sung-ho Park ,  Yo-sep Min ,  Jeong-hee Han

IPC分类号： H01L21/336

CPC分类号： H01L21/324 ,  H01L21/28273 ,  H01L21/28282

摘要： In a method of manufacturing a memory device having improved erasing characteristics, the method includes sequentially forming a tunneling oxide layer, a charge storing layer, and a blocking oxide layer on a semiconductor substrate; annealing the semiconductor substrate including the tunneling oxide layer, the charge storing layer, and the blocking oxide layer under a gas atmosphere so that the blocking oxide layer has a negative fixed oxide charge; forming a gate electrode on the blocking oxide layer with the negative fixed oxide charge and etching the tunneling oxide layer, the charge storing layer, and the blocking oxide layer to form a gate structure; and forming a first doped region and a second doped region in the semiconductor substrate at sides of the gate structure by doping the semiconductor substrate with a dopant.

摘要翻译： 在制造具有改善的擦除特性的存储器件的方法中，该方法包括在半导体衬底上依次形成隧穿氧化物层，电荷存储层和阻挡氧化物层; 在气体气氛下退火包括隧道氧化物层，电荷存储层和阻挡氧化物层的半导体衬底，使得阻挡氧化物层具有负的固定氧化物电荷; 在阻挡氧化物层上形成具有负固定氧化物电荷的栅电极，蚀刻隧道氧化物层，电荷存储层和阻挡氧化物层以形成栅极结构; 以及通过用掺杂剂掺杂半导体衬底，在栅极结构的侧面在半导体衬底中形成第一掺杂区和第二掺杂区。

公开(公告)号：US20060211205A1

公开(公告)日：2006-09-21

申请号：US11385642

申请日：2006-03-21

申请人： Sang-hun Jeon ,  Kyu-sik Kim ,  Chung-woo Kim ,  Sung-ho Park ,  Yo-sep Min ,  Jeong-hee Han

发明人： Sang-hun Jeon ,  Kyu-sik Kim ,  Chung-woo Kim ,  Sung-ho Park ,  Yo-sep Min ,  Jeong-hee Han

IPC分类号： H01L21/336

CPC分类号： H01L21/324 ,  H01L21/28273 ,  H01L21/28282

摘要： In a method of manufacturing a memory device having improved erasing characteristics, the method includes sequentially forming a tunneling oxide layer, a charge storing layer, and a blocking oxide layer on a semiconductor substrate; annealing the semiconductor substrate including the tunneling oxide layer, the charge storing layer, and the blocking oxide layer under a gas atmosphere so that the blocking oxide layer has a negative fixed oxide charge; forming a gate electrode on the blocking oxide layer with the negative fixed oxide charge and etching the tunneling oxide layer, the charge storing layer, and the blocking oxide layer to form a gate structure; and forming a first doped region and a second doped region in the semiconductor substrate at sides of the gate structure by doping the semiconductor substrate with a dopant.

摘要翻译： 在制造具有改善的擦除特性的存储器件的方法中，该方法包括在半导体衬底上依次形成隧穿氧化物层，电荷存储层和阻挡氧化物层; 在气体气氛下退火包括隧道氧化物层，电荷存储层和阻挡氧化物层的半导体衬底，使得阻挡氧化物层具有负的固定氧化物电荷; 在阻挡氧化物层上形成具有负固定氧化物电荷的栅电极，蚀刻隧道氧化物层，电荷存储层和阻挡氧化物层以形成栅极结构; 以及通过用掺杂剂掺杂半导体衬底，在栅极结构的侧面在半导体衬底中形成第一掺杂区和第二掺杂区。

公开(公告)号：US07358137B2

公开(公告)日：2008-04-15

申请号：US11245426

申请日：2005-10-07

申请人： Sang-hun Jeon ,  Chung-woo Kim ,  Hyun-sang Hwang

发明人： Sang-hun Jeon ,  Chung-woo Kim ,  Hyun-sang Hwang

IPC分类号： H01L21/336 ,  H01L29/788

CPC分类号： H01L21/28273 ,  H01L29/513 ,  H01L29/7881

摘要： Memory devices and methods of manufacturing the same are provided. Memory devices may include a substrate, a source region and a drain region and a gate structure. The gate structure may be in contact with the source and drain regions, and may include a barrier layer. The barrier layer may be formed of at least two layers. The at least two layers may have different bandgap energies.

摘要翻译： 提供了存储器件及其制造方法。 存储器件可以包括衬底，源极区域和漏极区域以及栅极结构。 栅极结构可以与源极和漏极区域接触，并且可以包括阻挡层。 阻挡层可以由至少两层形成。 至少两层可能具有不同的带隙能量。

公开(公告)号：US08217445B2

公开(公告)日：2012-07-10

申请号：US10864499

申请日：2004-06-10

申请人： Sang-hun Jeon ,  Soo-doo Chae ,  Ju-hyung Kim ,  Chung-woo Kim

发明人： Sang-hun Jeon ,  Soo-doo Chae ,  Ju-hyung Kim ,  Chung-woo Kim

IPC分类号： H01L29/792

CPC分类号： H01L21/28282

摘要： A SONOS memory device, and a method of manufacturing the same, includes a substrate and a multifunctional device formed on the substrate. The multifunctional device performs both switching and data storing functions. The multifunctional device includes first and second impurities areas, a channel formed between the first and second impurities areas, and a stacked material formed on the channel for data storage. The stacked material for data storage is formed by sequentially stacking a tunneling oxide layer, a memory node layer in which data is stored, a blocking layer, and an electrode layer.

摘要翻译： SONOS存储器件及其制造方法包括形成在衬底上的衬底和多功能器件。 多功能设备执行切换和数据存储功能。 多功能装置包括第一和第二杂质区域，形成在第一和第二杂质区域之间的通道，以及形成在通道上用于数据存储的堆叠材料。 用于数据存储的层叠材料通过依次层叠隧道氧化物层，存储数据的存储节点层，阻挡层和电极层而形成。

公开(公告)号：US07053448B2

公开(公告)日：2006-05-30

申请号：US11070090

申请日：2005-03-03

申请人： Sang-hun Jeon ,  Chung-woo Kim ,  Dong-joon Ma ,  Sung-kyu Choi

发明人： Sang-hun Jeon ,  Chung-woo Kim ,  Dong-joon Ma ,  Sung-kyu Choi

IPC分类号： H01L29/792

CPC分类号： H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/022 ,  H01L21/28282 ,  H01L21/31616 ,  H01L21/31645 ,  H01L28/56 ,  H01L29/513 ,  H01L29/792

摘要： A SONOS type memory includes a semiconductor substrate, first and second impurity regions in the semiconductor substrate doped with impurity ions of a predetermined conductivity, separated a predetermined distance from each other, a channel region between the first and second impurity regions, and a data storage type stack on the semiconductor substrate between the first and second impurity regions. The data storage type stack includes a tunneling oxide layer, a memory node layer for storing data, a blocking oxide layer, and an electrode layer, which are sequentially formed. A dielectric constant of the memory node layer is higher than dielectric constants of the tunneling and the blocking oxide layers, and a band offset of the memory node layer is lower than band offsets of the tunneling and the blocking oxide layers. The tunneling oxide layer and the blocking oxide layer are high dielectric insulating layers.

摘要翻译： SONOS型存储器包括半导体衬底，半导体衬底中掺杂有预定电导率的杂质离子的第一和第二杂质区，彼此隔开预定距离，第一和第二杂质区之间的沟道区，以及数据存储 在第一和第二杂质区之间的半导体衬底上。 数据存储型堆叠包括依次形成的隧道氧化物层，用于存储数据的存储节点层，阻挡氧化物层和电极层。 存储节点层的介电常数高于隧道和阻塞氧化物层的介电常数，并且存储器节点层的带偏移低于隧道和阻塞氧化物层的带偏移。 隧道氧化物层和阻挡氧化物层是高介电绝缘层。

公开(公告)号：US20070296026A1

公开(公告)日：2007-12-27

申请号：US11896698

申请日：2007-09-05

申请人： Sang-hun Jeon ,  Soo-doo Chae ,  Ju-hyung Kim ,  Chung-woo Kim

发明人： Sang-hun Jeon ,  Soo-doo Chae ,  Ju-hyung Kim ,  Chung-woo Kim

IPC分类号： H01L29/792

CPC分类号： H01L29/40117

摘要： A SONOS memory device, and a method of manufacturing the same, includes a substrate and a multifunctional device formed on the substrate. The multifunctional device performs both switching and data storing functions. The multifunctional device includes first and second impurities areas, a channel formed between the first and second impurities areas, and a stacked material formed on the channel for data storage. The stacked material for data storage is formed by sequentially stacking a tunneling oxide layer, a memory node layer in which data is stored, a blocking layer, and an electrode layer.

摘要翻译： SONOS存储器件及其制造方法包括形成在衬底上的衬底和多功能器件。 多功能设备执行切换和数据存储功能。 多功能装置包括第一和第二杂质区域，形成在第一和第二杂质区域之间的通道，以及形成在通道上用于数据存储的堆叠材料。 用于数据存储的层叠材料通过依次层叠隧道氧化物层，存储数据的存储节点层，阻挡层和电极层而形成。

公开(公告)号：US20060131636A1

公开(公告)日：2006-06-22

申请号：US11249396

申请日：2005-10-14

申请人： Sang-hun Jeon ,  Chung-woo Kim

发明人： Sang-hun Jeon ,  Chung-woo Kim

IPC分类号： H01L29/788

CPC分类号： H01L29/66825 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

摘要： A non-volatile memory device having an improved erase efficiency and a method of manufacturing the same are provided. The method includes: forming a stack structure of a tunnel dielectric layer, a charge trapping layer, a charge blocking layer and a gate on a semiconductor substrate; and performing a post treatment of the gate using an oxygen or CF4 plasma or ion implantation to increase a work function of an element forming the gate. Since the work function of the metal layer forming the gate can be further increased, an electron back tunneling can be suppressed during an erase operation.

摘要翻译： 提供了具有改进的擦除效率的非易失性存储器件及其制造方法。 该方法包括：在半导体衬底上形成隧道介电层，电荷俘获层，电荷阻挡层和栅极的堆叠结构; 以及使用氧或CF 4等离子体或离子注入来执行栅极的后处理以增加形成栅极的元件的功函数。 由于可以进一步增加形成栅极的金属层的功函数，所以可以在擦除操作期间抑制电子反向隧穿。

公开(公告)号：US08237214B2

公开(公告)日：2012-08-07

申请号：US11980352

申请日：2007-10-31

申请人： Wan-jun Park ,  Jo-won Lee ,  Sang-hun Jeon ,  Chung-woo Kim

发明人： Wan-jun Park ,  Jo-won Lee ,  Sang-hun Jeon ,  Chung-woo Kim

IPC分类号： H01L29/792

CPC分类号： H01L21/28273 ,  H01L21/28282

摘要： A non-volatile memory device including a metal-insulator transition (MIT) material is provided. The non-volatile memory device includes a gate stack having a tunneling layer, a charge trap layer, a blocking layer and a gate electrode formed on a substrate, wherein at least one of the tunneling layer and the blocking layer is formed of an MIT (metal-insulator transition) material.

摘要翻译： 提供了包括金属 - 绝缘体转变（MIT）材料的非易失性存储器件。 非易失性存储器件包括具有隧道层，电荷陷阱层，形成在衬底上的阻挡层和栅电极的栅极堆叠，其中隧道层和阻挡层中的至少一个由MIT形成 金属 - 绝缘体转变）材料。